AM29LV320DT90EI AMD (ADVANCED MICRO DEVICES), AM29LV320DT90EI Datasheet - Page 23

• Manufacturer Part Number: AM29LV320DT90EI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV320DT90EI

• Memory Configuration: 4M X 8 / 2M X 16 Bit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadver tent writes (refer to Table 14 on
page 29 for command definitions). In addition, the fol-
lowing hardware data protection measures prevent ac-
cidental erasure or programming, which might
otherwise be caused by spurious system level signals
during V
from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V
system must provide the proper signals to the control
pins to prevent unintentional writes when V
greater than V
December 14, 2005
Figure 3. Secured Silicon Sector Protect Verify
CC
CC
CC
Write Inhibit
Write 40h to SecSi
Read from SecSi
is less than V
Sector address
Sector address
power-up and power-down transitions, or
A1 = 1, A0 = 0
A1 = 1, A0 = 0
Write 60h to
with A6 = 0,
any address
with A6 = 0,
RESET# =
V
Wait 1 μs
LKO
START
IH
or V
.
ID
LKO
CC
, the device does not ac-
is greater than V
Remove V
SecSi Sector is
SecSi Sector is
If data = 00h,
If data = 01h,
from RESET#
Protect Verify
SecSi Sector
unprotected.
Write reset
protected.
command
complete
IH
or V
ID
D A T A S H E E T
LKO
. The
CC
Am29LV320D
CC
is
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The sys-
tem can read CFI information at the addresses given
in Table 9 on page 22 through Table 12 on page 24. To
terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 9 on page 22
through Table 12 on page 24. The system must write
the reset command to return the device to the reading
array data.
For further information, please refer to the CFI Specifi-
cation, CFI Publication 100, and the application note
“Common Flash Interface Version 1.4 Vendor Specific
Extensions”. Contact an AMD representative for cop-
ies of these documents.
IL
, CE# = V
IH
or WE# = V
IL
and OE# = V
IH
. To initiate a write cycle,
IH
during power up,
21