AM29LV320DT90EI AMD (ADVANCED MICRO DEVICES), AM29LV320DT90EI Datasheet - Page 29

• Manufacturer Part Number: AM29LV320DT90EI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV320DT90EI

• Memory Configuration: 4M X 8 / 2M X 16 Bit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 14 on
page 29 shows the address and data requirements for
the chip erase command sequence. Note that the au-
toselect, Secured Silicon sector, and CFI modes are
unavailable while an erase operation is in progress.
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
December 14, 2005
Note: See Table 14 on page 29 for program command
sequence.
Increment Address
Figure 4. Program Operation
Embedded
in progress
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
D A T A S H E E T
No
Am29LV320D
RY/BY#. Refer to “Write Operation Status” on page 30
for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device returns to reading array
data, to ensure data integrity.
Figure 5, on page 28
erase operation. Refer to table “Erase and Program
Operations” on page 41 for parameters, and
19, on page 43
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 14 on page 29
shows the address and data requirements for the sec-
tor erase command sequence. Note that the autose-
lect, Secured Silicon sector, and CFI modes are
unavailable while an erase operation is in progress.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than
50 µs, otherwise the last address and command may
not be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sec to r Er as e or Er as e Su sp end dur in g th e
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer timed out (See the section “DQ3: Sec-
tor Erase Timer” on page 32.). The time-out begins
from the rising edge of the final WE# pulse in the com-
mand sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6,
section for timing diagrams.
illustrates the algorithm for the
Figure
27