MT9V022IA7ATM Aptina LLC, MT9V022IA7ATM Datasheet
MT9V022IA7ATM
Specifications of MT9V022IA7ATM
Available stocks
Related parts for MT9V022IA7ATM
MT9V022IA7ATM Summary of contents
Page 1
... IBGA, automotive-qualified; wafer or die Ordering Information Table 2: Available Part Numbers Part Number MT9V022I77ATM 52-Ball IBGA (monochrome) MT9V022IA7ATM 52-Ball IBGA (lead-free monochrome) MT9V022I77ATC 52-Ball IBGA (color) MT9V022IA7ATC 52-Ball IBGA (lead-free color) Aptina reserves the right to change products or specifications without notice. 1 Features ...
Page 2
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of Figures Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
List of Tables Table 1: Key Performance Parameters ...
Page 6
General Description The Aptina sensor with global shutter and high dynamic range (HDR) operation. The sensor has specifically been designed to support the demanding interior and exterior automotive imaging needs, which makes this part ideal for a wide variety of ...
Page 7
Figure 2: 52-Ball IBGA Package PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor SER_ SER_ SYS- DATAOUT DATAOUT ...
Page 8
Ball Descriptions Table 3: Ball Descriptions Only pins D 0 through D OUT 52-Ball IBGA Numbers Symbol H7 RSVD D2 SER_DATAIN_N D1 SER_DATAIN_P C2 BYPASS_CLKIN_N C1 BYPASS_CLKIN_P H3 EXPOSURE H4 SCLK S_CTRL_ADR0 H8 S_CTRL_ADR1 G8 RESET# F8 ...
Page 9
Table 3: Ball Descriptions (continued) Only pins D 0 through D OUT 52-Ball IBGA Numbers Symbol A2 SER_DATAOUT_P B4 C8 VAAPIX A1 LVDS DD B1, C3 LVDSGND C6 GND ...
Page 10
Pixel Data Format Pixel Array Structure The MT9V022 pixel array is configured as 782 columns by 492 rows, shown in Figure 4. The left 26 columns and the top eight rows of pixels are optically black and can be used ...
Page 11
Color Device Limitations The color version of the MT9V022 does not support or offers reduced performance for the following functionalities. Pixel Binning Pixel binning is done on immediate neighbor pixels only, no facility is provided to skip pixels according to ...
Page 12
Figure 6: Spatial Illustration of Image Readout P m-1,0 PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor .....................................P 0,0 0,1 0,2 0,n .....................................P 1,0 1,1 1,2 1,n-1 VALID IMAGE ...
Page 13
Output Data Timing The data output of the MT9V022 is synchronized with the PIXCLK output. When LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period. Figure 7: Timing Example of Pixel Data LINE_VALID PIXCLK Blanking D (9:0) ...
Page 14
Table 4: Frame Time (continued) Parameter Name A+Q Row time V Vertical blanking Nrows Frame valid time F Total frame time Sensor timing is shown above in terms of pixel clock and master clock cycles (refer ...
Page 15
Serial Bus Description Registers are written to and read from the MT9V022 through the two-wire serial inter- face bus. The MT9V022 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0 and 0xB8) determined by the S_CTRL_ADR0 and ...
Page 16
Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line ...
Page 17
Two-Wire Serial Interface Sample Read and Write Sequences 16-Bit Write Sequence A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit given by the master, followed by the write address, starts ...
Page 18
Write Sequence To be able to write 1 byte at a time to the register a special register address is added. The 8-bit write is done by first writing the upper 8 bits to the desired register and then ...
Page 19
Register Lock Included in the MT9V022 is a register lock (R0xFE) feature that can be used as a solution to reduce the probability of an inadvertent noise-triggered two-wire serial interface write to the sensor. All registers (or read mode register—register ...
Page 20
Feature Description Operational Modes The MT9V022 works in master, snapshot, or slave mode. In master mode the sensor generates the readout timing. In snapshot mode it accepts an external trigger to start integration, then generates the readout timing. In slave ...
Page 21
When exposure time is greater than the sum of vertical blank and window height, the number of vertical blank rows is increased automatically to accommodate the exposure time. Sequential Master Mode In sequential master mode the exposure period is followed ...
Page 22
Figure 17: Snapshot Mode Frame Synchronization Waveforms EXPOSURE LED_OUT FRAME_VALID LINE_VALID D (9:0) OUT Slave Mode In slave mode, the exposure and readout are controlled using the EXPOSURE, STFRM_OUT, and STLN_OUT pins. When the slave mode is enabled, STFRM_OUT and ...
Page 23
Signal Path The MT9V022 signal path consists of a programmable gain, a programmable analog offset, and a 10-bit ADC. See “Black Level Calibration” on page 30 for the programmable offset operation description. Figure 19: Signal Path Offset Correction Voltage (R0x48 ...
Page 24
Window Control Registers R0x01 column start, R0x02 Row Start, R0x03 window height (row size), and R0x04 Window Width (column size) control the size and starting coordinates of the window. The values programmed in the window height and width registers are ...
Page 25
Changes to Integration Time With automatic exposure control disabled (R0xAF, bit 0 is cleared to LOW), and if the total integration time (R0x0B) is changed via the two-wire serial interface while FRAME_VALID is asserted for frame n, the first frame ...
Page 26
Exposure Indicator The exposure indicator is controlled by: • R0x1B LED_OUT Control The MT9V022 provides an output pin, LED_OUT, to indicate when the exposure takes place. When R0x1B bit 0 is clear, LED_OUT is HIGH during exposure. By using R0x1B, ...
Page 27
The parameters of the step voltage V_Step which takes values V1, V2, and V3 directly affect the position of the knee points in Figure 22. Light intensities work approximately as a reciprocal of the partial exposure time. Typi- cally, shortest ...
Page 28
Figure 23: 12- to 10-Bit Companding Chart 10-bit Codes 1,024 768 512 256 Gain Settings Changes to Gain Settings When the digital gain settings (R0x80 next frame start. However, the latency for an analog gain change to take effect depends ...
Page 29
Analog Gain Analog gain is controlled by: • R0x35 Global Gain The formula for gain setting is: The analog gain range supported in the MT9V022 is 1X 6.25 percent. To control gain manually with this register, the sensor must NOT ...
Page 30
Registers 0x99 Figure 25, respectively. Digital gains of registers 0x80 supports a digital gain of 0.25-3.75X. The formula for digital gain setting is: Black Level Calibration Black level calibration is controlled by: • R0x4C • R0x42 • R0x46–R0x48 The MT9V022 ...
Page 31
In normal operation, the black level calibration value/offset correction value is calcu- lated at the beginning of each frame and can be read through the two-wire serial inter- face from R0x48. This register is an 8-bit signed two’s complement value. ...
Page 32
Automatic Gain Control and Automatic Exposure Control The integrated AEC/AGC unit is responsible for ensuring that optimal auto settings of exposure and (analog) gain are computed and updated every frame. AEC and AGC can be individually enabled or disabled by ...
Page 33
Hard Reset of Logic The RC circuit for the MT9V022 uses a 10kΩ resistor and a 0.1μF capacitor. The rise time for the RC circuit is 1μs maximum. Soft Reset of Logic Soft reset of logic is controlled by: • ...
Page 34
Read Mode Options (Also see “Output Data Format” on page 11 and “Output Data Timing” on page 13.) Column Flip By setting bit 5 of R0x0D the readout order of the columns is reversed, as shown in Figure 28 on ...
Page 35
Row Binning By setting bit R0x0D, only half or one-fourth of the row set is read out, as shown in figure below. The number of rows read out is half or one-fourth of what is set ...
Page 36
Interlaced Readout The MT9V022 has two interlaced readout options. By setting R0x07[2: all the even- numbered rows are read out first, followed by a number of programmable field blanking (R0xBF, bits 7:0), and then the odd-numbered rows and ...
Page 37
LINE_VALID By setting bit 2 and 3 of R0x74 the LINE_VALID signal can get three different output formats. The formats for reading out four rows and two vertical blanking rows are shown in Figure 33. In the last format, the ...
Page 38
Figure 34: Serial Output Format for a 6x2 Frame Internal PIXCLK Internal P Parallel Data Internal Line_Valid Internal Frame_Valid External Serial Data Out Notes: 1. External pixel values are reserved (they only convey control information). ...
Page 39
Table 8: LVDS Packet Format in Stereoscopy Mode (Stereoscopy Mode Bit Asserted) Control signals LINE_VALID and FRAME_VALID can be reconstructed from their respec- tive preceding and succeeding flags that are always embedded within the pixel data in the form of ...
Page 40
Electrical Specifications Table 10: DC Electrical Characteristics V = 3.3V ±0.3V Ambient = 25 PWR A Symbol Definition V Input high voltage IH V Input low voltage IL I Input leakage current IN V Output high voltage OH ...
Page 41
Table 11: Absolute Maximum Ratings Caution Stresses greater than those listed may cause permanent damage to the device. Symbol V Power supply voltage (all supplies) SUPPLY I Total power supply current SUPPLY I Total ground current GND V DC input ...
Page 42
Propagation Delays for FRAME_VALID and LINE_VALID Signals The LINE_VALID and FRAME_VALID signals change on the same rising master clock edge as the data output. The LINE_VALID goes HIGH on the same rising master clock edge as the output of the ...
Page 43
Performance Specifications Table 13 summarizes the specification for each performance parameter. Table 13: Performance Specifications Parameter Unit Sensitivity DSNU PRNU Dynamic Range SNR Notes: 1. All specifications address operation tested without a lens. Multiple images were captured ...
Page 44
Test 4: Dynamic Range A temporal noise measurement is made with the image sensor in the dark and analog gain changed to the maximum setting of 4X. Signals are measured in LSB on the sensor output. Two consecutive dark frames ...
Page 45
Two-Wire Serial Bus Timing The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles. Figure 37: Serial Host Interface Start Condition Timing SCLK S DATA Figure ...
Page 46
Figure 41: Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor SCLK S DATA Figure 42: Acknowledge Signal Timing After an 8-Bit READ from the Sensor SCLK S DATA Note: After a READ, the master receiver must pull down ...
Page 47
Figure 43: Typical Quantum Efficiency—Color Figure 44: Typical Quantum Efficiency—Monochrome PDF: 3295348826/Source:7478516499 MT9V022_DS - Rev.H 6/10 EN MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor 350 ...
Page 48
Package Dimensions Figure 45: 52-Ball IBGA D Seating plane A 0.10 A 52X Ø0.55 7.00 Dimensions apply to solder balls post 1.00 TYP reflow. The pre- Ball A8 reflow ball is Ø0. Ø0.4 NSMD ball pad. 3.50 7.00 ...
Page 49
Appendix A – Serial Configurations With the LVDS serial video output, the deserializer can meters from the sensor. The serial link can save on the cabling cost of 14 wires (D FRAME_VALID, PIXCLK, GND). Instead, just ...
Page 50
Configuration of Sensor for Stereoscopic Serial Output with Internal PLL In this configuration the internal PLL generates the shift-clk (x18) in phase with the system-clock. The LVDS pins SER_DATAOUT_P and SER_DATAOUT_N must be connected to a deserializer (clocked at approximately ...
Page 51
Broadcast and Individual Writes for Stereoscopic Topology In stereoscopic mode, the two sensors are required to run in lockstep. This implies that control logic in each sensor is in exactly the same state as its pair on every clock. To ...
Page 52
Appendix B – Power-On Reset and Standby Timing Reset, Clocks, and Standby There are no constraints concerning the order in which the various power supplies are applied; however, the MT9V022 requires reset in order operate properly at power-up. Refer to ...
Page 53
Standby Assertion Restrictions STANDBY cannot be asserted at any time. If STANDBY is asserted during a specific window within the vertical blanking period, the MT9V022 may enter a permanent standby state. This window (that is, dead zone) occurs prior to ...
Page 54
Revision History Rev ...
Page 55
Updated Table 7, “Default Register Descriptions,” on page 15. Updated Registers 0x00, 0x0D, 0xF0, 0xF1 and 0xFF. Updated Registers 0x10, 0x15, 0x20 and 0xC2 with Rev 3 default values. • Updated Table 8, “Register Descriptions,” on page 19 0x00, ...
Page 56
Rev ...