MT9V022IA7ATM Aptina LLC, MT9V022IA7ATM Datasheet - Page 22

• Manufacturer Part Number: MT9V022IA7ATM
• Description: SENSOR IMAGE VGA MONO 52IBGA
• Manufacturer: Aptina LLC
• Type: CMOS Imagingr
• Series: DigitalClarity®r

Specifications of MT9V022IA7ATM

• Pixel Size: 6µm x 6µm
• Active Pixel Array: 752H x 480V
• Frames Per Second: 60
• Voltage - Supply: 3.3V
• Package / Case: 52-IBGA
• Sensor Image Color Type: Monochrome
• Sensor Image Size Range: 250,920 to 480,000Pixels
• Sensor Image Size: 752x480Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Package Type: IBGA
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1205

Figure 17:
Slave Mode
Figure 18:
PDF: 3295348826/Source:7478516499
MT9V022_DS - Rev.H 6/10 EN
Snapshot Mode Frame Synchronization Waveforms
Slave Mode Operation
FRAME_VALID
LINE_VALID
EXPOSURE
LED_OUT
D
In slave mode, the exposure and readout are controlled using the EXPOSURE,
STFRM_OUT, and STLN_OUT pins. When the slave mode is enabled, STFRM_OUT and
STLN_OUT become input pins.
The start and end of integration are controlled by EXPOSURE and STFRM_OUT pulses,
respectively. While a STFRM_OUT pulse is used to stop integration, it is also used to
enable the readout process.
After integration is stopped, the user provides STLN_OUT pulses to trigger row readout.
A full row of data is read out with each STLN_OUT pulse. The user must provide enough
time between successive STLN_OUT pulses to allow the complete readout of one row.
It is also important to provide additional STLN_OUT pulses to allow the sensors to read
the vertical blanking rows. It is recommended that the user program the vertical blank
register (R0x06) with a value of 4, and achieve additional vertical blanking between
frames by delaying the application of the STFRM_OUT pulse.
The elapsed time between the rising edge of STLN_OUT and the first valid pixel data is
[horizontal blanking register (R0x05) + 4] clock cycles.
OUT
(9:0)
STFRM_OUT
LINE_V ALID
STLN_OUT
Exposure
LED_OUT
(output)
(input)
(output)
xxx
(input)
(input)
1-row
time
22
Integration T ime
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
xxx
2 master
clocks
Aptina reserves the right to change products or specifications without notice.
1-row
time
Vertical Blanking
(def = 45 lines)
Exposure Time
©2005 Aptina Imaging Corporation. All rights reserved.
Feature Description
98 ma ster
clocks
xxx