CYIL2SM1300AA-GZDC Cypress Semiconductor Corp, CYIL2SM1300AA-GZDC Datasheet - Page 11

• Manufacturer Part Number: CYIL2SM1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-3
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SM1300AA-GZDC

• Package / Case: 168-PGA
• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Operating Supply Voltage: 2.5 V
• Maximum Power Dissipation: 1350 mW
• Maximum Operating Temperature: + 70 C
• Supply Current: 80 mA
• Minimum Operating Temperature: 0 C
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 13. Internal Registers (continued)
Document Number: 001-24599 Rev. *C
LVDS clk
divider
AFE
Bias block
Image Core
Block
lvdsmain
lvdspwd1
lvdspwd2
Fix6
afebias
afemode
afepwd1
afepwd2
bandgap
Fix7
Fix8
imcbias1
imcbias2
imcbias3
Imcbias4
imcmodes
Register Name
Address [6..0]
10
11
12
13
14
15
16
17
18
19
20
5
6
7
8
9
Field
[3:0]
[7:4]
[7:0]
[5:0]
[7:0]
[3:0]
[2:0]
[5:3]
[7:0]
[3:0]
[5:3]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[6]
[7]
[6]
[0]
[1]
[2]
[0]
[1]
[2]
[3]
[4]
[5]
‘0110’
0
0x00
0
0
0
0x00
‘1000’
‘111’
‘000’
0
0x00
0x00
‘0’
‘1’
‘0’
‘000’
0
‘1’
‘1’
0
‘1’
‘0’
0x00
0x00
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
Reset Value
lvds trim
clkadc phase
Power down channel 7:0
Power down channel 13:8
Power down all channels
lvds test mode
Reserved, fixed value
afe current biasing
vrefp, vrefm settings
Pga settings
Power down AFE
Power down adc_channel_2x 7 to 0
Power down adc_channel_2x 11 to 8
Power down bandgap and currents
External resistor
External voltage reference
Bandgap trimming
Power down
Enable vrefcol regulator
Enable precharge regulator
Disable internal bias for vprech
Disable column load
clkmain invert
Reserved, fixed value
Reserved, fixed value
Bias colfpn DAC buffer
Bias precharge regulator
Bias pixel precharge level
Bias column ota
Bias column unip fast
Bias column unip slow
Bias column load
Bias column precharge
Description
CYIL2SM1300AA
Page 11 of 41
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