CYIL2SM1300AA-GZDC Cypress Semiconductor Corp, CYIL2SM1300AA-GZDC Datasheet - Page 19

• Manufacturer Part Number: CYIL2SM1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-3
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SM1300AA-GZDC

• Package / Case: 168-PGA
• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Operating Supply Voltage: 2.5 V
• Maximum Power Dissipation: 1350 mW
• Maximum Operating Temperature: + 70 C
• Supply Current: 80 mA
• Minimum Operating Temperature: 0 C
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Programming the Exposure Time
In master mode, the exposure time is configured in two distinct methods (controlled by register seqmode3[6]):
■
■
Table 14
Table 14. User Programmable Timer Settings
Note that the seqmode3[7] can also be used to sync the user signals in slave mode. The behavior is exactly the same.
Master Mode
In master mode the reset and exposure time is written in registers.
Ensure that the added value of the registers res_length and tint_timer always exceeds the number of lines that are read out. This is
because the sequencer samples a new image after integration is complete, without checking if image readout is finished. Enlarging
res_length to accommodate for this has no impact on image capture.
Document Number: 001-24599 Rev. *C
reg_res_length
reg_tint_timer
reg_tint_ds_timer
reg_tint_ts_timer
reg_rot_timer
reg_fot_timer
reg_sel_pre_timer
reg_precharge_timer
reg_sample_timer
reg_vmem_timer
reg_delayed_rdt_timer
#lines: Obvious, changing signals that control integration time. They are always changed during ROT to avoid any image artefacts.
#clock cycles: Must be multiplied by (2**seqmode4[3:0]). When the counter expires, changes are put into effect immediately. Asserting
the configuration signal (seqmode3[7]) forces delaying signal updates until the next ROT.
lists the user programmable timer settings and how they are interpreted by the hardware.
Setting
Lines/cycles
Lines/cycles
Lines/cycles
Lines/cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
Lines/cycles
Figure 13. Integration and Image Readout in Master Mode
Granularity
CYIL2SM1300AA
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