ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 13

• Manufacturer Part Number: ISPPAC-CLK5620V-01TN100I
• Description: Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

• Max Input Freq: 320 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Timing Diagrams
Figure 7. Erase (User Erase or Erase All) Timing Diagram
Figure 8. Programming Timing Diagram
Figure 9. Verify Timing Diagram
Figure 10. Discharge Timing Diagram
State
TCK
TMS
TMS
TCK
State
State
TCK
TMS
State
TCK
TMS
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
Update-IR
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
Update-IR
t
SU1
Update-IR
Update-IR
t
SU1
t
SU1
t
SU1
t
CKH
t
t
H
CKH
t
H
Run-Test/Idle (Erase or Program)
t
SU1
t
CKH
t
t
t
SU1
CKH
CKL
t
t
t
GKL
H
H
Run-Test/Idle (Erase)
t
SU1
t
SU1
t
t
CKL
CKL
t
Run-Test/Idle (Program)
H
Run-Test/Idle (Program)
t
H
The clock (TCK) must be
able to run free with TMS = VIL
t
PWP
The clock (TCK) must be
able to run free with TMS = VIL
The clock (TCK) must be
able to run free with TMS=VIL
t
t
t
H
H
or t
BEW
BEW
t
t
SU1
SU1
t
PWP
t
PWV
Select-DR Scan
Select-DR Scan
t
t
CKH
CKH
t
t
t
t
SU1
H
SU1
H
13
t
Select-DR Scan
Select-DR Scan
t
CKH
CKH
t
t
H
H
t
SU1
t
SU1
t
HVDIS
ispClock5600 Family Data Sheet
t
CKH
(Actual)
t
t
H
CKH
t
H
t
Run-Test/Idle (Discharge)
The clock (TCK) must be
able to run free with TMS = VIL
t
t
SU1
SU1
SU1
t
GKL
t
Run-Test/Idle (Verify)
SU1
t
CKL
t
CKH
Specified by the Data Sheet
t
t
t
CKH
CKH
H
t
Update-IR
Update-IR
Specified by the Data Sheet
CKH
t
t
H
H
t
H
t
SU2
t
t
SU1
SU1
t
t
PWV
t
CKL
CKL
t
SU1
t
Actual
SU1
t
PWV
t
t
CKH
CKH
t
t
H
t
H
CKH
t
H
t
CKH
t
H