ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 8

• Manufacturer Part Number: ISPPAC-CLK5620V-01TN100I
• Description: Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

• Max Input Freq: 320 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Output Test Loads
Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other
selected parameters as noted in the various tables of this data sheet.
Figure 3. CMOS Termination Load
Figure 4. HSTL/SSTL Termination Load
Figure 5. LVDS/LVPECL Termination Load
ispCLOCK
ispCLOCK
Zo = HSTL: ~20Ω
50Ω/3"
50Ω/3"
ispCLOCK
SSTL: 40Ω
50Ω/1"
50Ω/1"
Zo = 50Ω
50Ω/3"
(parasitic)
33.2Ω
33.2Ω
(parasitic)
Interface Circuit
50Ω/3"
3pF
3pF
50Ω/36"
44.2Ω
8
34Ω
34Ω
50Ω/36"
0.1U
0.1U
50Ω
ispClock5600 Family Data Sheet
950Ω
50Ω/36"
50Ω/36"
SCOPE
50Ω 5pF
950Ω
VTERM
ChA
ChB
SCOPE
50Ω 5pF
SCOPE
50Ω
50Ω
5pF
5pF