ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 14

• Manufacturer Part Number: ISPPAC-CLK5620V-01TN100I
• Description: Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

• Max Input Freq: 320 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Typical Performance Characteristics
-100
100
-50
-75
-25
75
50
25
25
20
15
10
1.2
0.8
0.6
0.4
0.2
0
5
0
320
1
0
*PFD = Phase/Frequency Detector
300
0
370
Cycle-Cycle Jitter vs. VCO Frequency
(Skew Mode = FINE, f
Typical Skew Error vs. Setting
3
400
(Normalized to 640MHz)
420
VCO Frequency (MHz)
I
Skew Setting #
CCD
6
f
VCO
470
V=4
vs. f
500
(MHz)
VCO
520
VCO
9
= 600MHz)
570
600
12
620
PFD =
20 MHz
40 MHz
80 MHz
700
15
14
1.2
0.8
0.6
0.4
0.2
70
65
60
55
50
40
35
30
45
25
20
15
10
1
0
5
0
320
320
0
PFD = 40MHz
(LVCMOS 3.3V, Normalized to 320MHz)
PFD = 20MHz
5 0
370
370
Period Jitter vs. VCO Frequency
Phase Jitter vs. VCO Frequency
ispClock5600 Family Data Sheet
I
CCO
100
420
420
Output Frequency (MHz)
VCO Frequency (MHz)
VCO Frequency (MHz)
vs. Output Frequency
PFD = 40MHz
150
470
470
V=4
V=4
PFD* = 20MHz
PFD = 80MHz
PFD = 80MHz
200
520
520
250
570
570
300
620
620
350