ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 7

Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN

ISPPAC-CLK5620V-01TN100I

Manufacturer Part Number
ISPPAC-CLK5620V-01TN100I
Description
Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
Manufacturer
Lattice
Type
Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

Max Input Freq
320 MHz
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPPAC-CLK5620V-01TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Switching Characteristics – Timing Adders for I/O Modes
t
LVTTL_in
LVCMOS18_in
LVCMOS25_in
LVCMOS33_in
SSTL2_in
SSTL3_in
HSTL_in
LVDS_in
LVPECL_in
t
LVTTL_out
LVCMOS18_out
LVCMOS25_out
LVCMOS33_out
SSTL2_out
SSTL3_out
HSTL_out
LVDS_out
LVPECL_out
t
Slew_1
Slew_2
Slew_3
Slew_4
1. Measured under standard output load conditions – see Figures 3-5.
2. All input adders referenced to LVTTL.
3. All output adders referenced to LVPECL.
Output Rise and Fall Times – Typical Values
IOI
IOO
IOS
LVTTL
LVCMOS 1.8V
LVCMOS 2.5V
LVCMOS 3.3V
SSTL2
SSTL3
HSTL
LVDS
LVPECL
1. See Figures 3-5 for test conditions.
2. Measured between 20% and 80% points.
3. Only the ‘fastest’ slew rate is available in LVDS and LVPECL modes.
Output Type
Input Adders
Output Slew Rate Adders
Output Adders
Adder Type
3
3
2
1, 3
Slew 1 (Fastest)
0.65
0.90
0.70
0.65
0.65
0.65
0.85
0.25
0.20
t
R
Using LVTTL Standard
Using LVCMOS 1.8V Standard
Using LVCMOS 2.5V Standard
Using LVCMOS 3.3V Standard
Using SSTL2 Standard
Using SSTL3 Standard
Using HSTL Standard
Using LVDS Standard
Using LVPECL Standard
Output Configured as LVTTL Buffer
Output Configured as LVCMOS 1.8V Buffer
Output Configured as LVCMOS 2.5V Buffer
Output Configured as LVCMOS 3.3V Buffer
Output Configured as SSTL2 Buffer
Output Configured as SSTL3 Buffer
Output Configured as HSTL Buffer
Output Configured as LVDS Buffer
Output Configured as LVPECL Buffer
Output Slew_1 (Fastest)
Output Slew_2
Output Slew_3
Output Slew_4 (Slowest)
1
0.45
0.40
0.40
0.45
0.40
0.40
0.30
0.20
0.20
t
F
0.85
1.05
0.90
0.85
0.90
0.90
1.00
t
Description
R
Slew 2
0.60
0.50
0.55
0.60
0.60
0.60
0.50
t
F
7
1.20
1.40
1.20
1.20
1.35
1.35
1.50
t
R
1, 2
Slew 3
ispClock5600 Family Data Sheet
0.90
0.80
0.85
0.90
0.85
0.85
0.70
t
F
-0.10
-0.15
-0.10
-0.10
-0.10
-0.10
Min.
0.20
1.15
1.15
1.15
1.15
1.15
0
0
0
0
0
0
Slew 4 (Slowest)
1.75
2.00
1.80
1.75
2.30
2.30
2.55
t
R
1320
Typ.
0.45
1.35
1.35
1.35
1.35
1.35
0.15
0.15
0.15
0.15
0.15
0.15
0.15
330
660
0
0
0
0
0
0
1.30
1.20
1.20
1.30
1.40
1.40
1.10
t
F
Max.
0.70
1.60
1.60
1.60
1.60
1.60
0.45
0.55
0.45
0.45
0.45
0.45
0.45
0
0
0
0
0
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps

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