ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 32

• Manufacturer Part Number: ISPPAC-CLK5620V-01TN100I
• Description: Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

• Max Input Freq: 320 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 26. Output Timing Adders for Logic Type (a) and Output Slew Rate (b)
Similarly, when one changes the slew rate of an output, the output slew rate adders (t
the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are
measured. For example, in the case of outputs configured to the same logic type (e.g. LVCMOS 1.8V), if one output
is set to the fastest slew rate (1, t
660ps of skew between the two outputs, as shown in Figure 26b.
Static Phase Offset and Input-Output Skew
The ispClock5600’s external feedback inputs can be used to obtain near-zero effective delays from the clock refer-
ence input pins to a designated output pin. In external feedback mode (Figure 27) the PLL will attempt to force the
output phase so that the rising edge phase (t φ) at the feedback input matches the rising edge phase at the refer-
ence input. The residual error between the two is specified as the static phase error. Note that any propagation
delays (t
the output. For this reason, if zero input-to-output delays are required in external feedback mode, the length of the
signal path between the output pin and the feedback pin should be minimized.
Figure 27. External Feedback Mode and Timing Relationships
Other Features
Internal Feedback Mode
In addition to supporting the use of external feedback to close the phase-locked loop, ispClock5620 also provides
the option of using an internal feedback path for this function. This feature is useful for minimizing external connec-
tions and routing in situations where one does not wish to attempt to compensate for external signal path delays.
LVPECL Output
(T
LVTTL Output
FBK
(T
IOS
IOS
) in the external feedback path drive the phase of the output signal backwards in time as measured at
= 0.1ns)
= 0)
Input Reference Clock
(a)
OUTPUT
IOS
BANK
REF
FBK
0.15ns
= 0ps), and another set to slew rate 3 (t
FBK
REF
32
t
t
FBK
φ
LVCMOS Output
LVCMOS Output
ispClock5600
(Slew rate=1)
(Slew rate=3)
Delay = t
FBK
OUTPUT
BANK
ispClock5600 Family Data Sheet
IOS
= 660ps), then one could expect
(b)
660ps
IOS
) can be used to predict