ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 18

• Manufacturer Part Number: ISPPAC-CLK5620V-01TN100I
• Description: Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

• Max Input Freq: 320 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 12. PLL Loop Bandwidth vs. Feedback Divider Setting (nominal)
VCO
The ispClock5600 provides an internal VCO which provides an output frequency ranging from 320MHz to 640MHz.
The VCO is implemented using differential circuit design techniques which minimize the influence of power supply
noise on measured output jitter. The VCO is also used to generate skews as a function of the total VCO period.
Using the VCO as the basis for controlling output skew allows for highly precise and consistent skew generation,
both from device-to-device, as well as channel-to-channel within the same device.
M, N, and V Dividers
The ispClock5600 incorporates a set of programmable dividers which provide the ability to synthesize output fre-
quencies differing from that of the reference clock input.
The input, or M divider prescales the input reference frequency, and can be programmed with integer values over
the range of 1 to 32. To achieve low levels of output jitter, it is best to use the smallest M divider value possible.
The feedback, or N divider prescales the feedback frequency and like the M divider, can also be programmed with
integer values ranging from 1 to 32.
Each one of the five output, or V dividers can be independently programmed to provide even division ratios ranging
from 2 to 64.
When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (f
culated as:
where
Note that because the feedback may be taken from any V divider, V
f
f
M and N are the input and feedback divider settings
V
V
k
ref
fbk
k
is the frequency of V divider k
is the setting of the V divider used to provide output k
is the input reference frequency
is the setting of the V divider used to close the PLL feedback path
1.75
1.25
0.75
0.25
1.5
0.5
0
1
2
0
*loop filter configured to recommended setting
Feedback Divider Setting* (Typical)
N x V Feedback Division Product
f
k
PLL Loop Bandwidth vs.
16
=
f
ref
18
N x V
M x V
32
fbk
k
k
and V
48
ispClock5600 Family Data Sheet
fbk
may refer to the same divider.
64
k
) may be cal-
(1)