CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet
CY7C955-NC
Specifications of CY7C955-NC
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CY7C955-NC Summary of contents
Page 1
... The CY7C955 can be used in a Network Interface Card (NIC) design to connect the segmentation and Reassembly (SAR) chip to the optical modules or equalizer chip. The CY7C955 can also be used in work group or enterprise switches to connect the I/O FIFOs of the switch fabric to the optical module or equalizer in the interface boards. ...
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... Configuration and Status ALE Controller RDB Interface WRB CSB INTB RSTB Receive UTOPIA I/F ATM Cell RALM Receive FIFO Processor 4 Cell by 8 bit Pin Descriptions CY7C955 ATM-SONET/SDH Transceiver Transmit Utopia Interface Name Pin I/O TDAT[7: Input TPRTY 95 Input TSOC 96 Input TFCLK 84 Input ...
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... TCLK. Description Receive Input Data: These line receiver inputs are connected to an internal Receive PLL that recovers the embedded clock and data information. The incoming data rate can be within one of two frequency ranges depending on the state of the RATE0 pin. 3 CY7C955 ...
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... Receive Utopia Enable: Enables the RFCLK input for data transfers from the AX. Receive Utopia Cell Available: An active signal indicates that the Receive FIFO con- tains at least more bytes of data. RCA is controlled by RCAINV (Reg 01H, bit 2) and RCALEVEL0 (Reg 59H, bit 2). 4 CY7C955 ...
Page 5
... ALOS+ is tied to GND. ALOS has to be decoupled. Reset: This active LOW signal provides a device reset. This line can be pulled LOW to put the CY7C955 into the power-down mode. RSTB has an integrated pull-up resis- tor. Factory test pin. Must be LOW for normal operation. VCLK has an integrated pull-down resistor ...
Page 6
... These Analog Test Points (ATPx) are for factory testing use only. These pins have to be ATP2, 46 tied to GND for correct chip operation. ATP3 PRELIMINARY . DDO . DDI ) pins should be connected to GND in common with V SSI ) pins should be connected to GND in common with V SSO 6 CY7C955 SSO . SSI ...
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... ALOS+ 28 RAVS3 29 RAVD1 30 RAVS1 31 RAVD4 32 RRCLK– 33 RRCLK+ 34 RAVS4 35 RAVD2 36 RAVS2 37 VSS 38 PRELIMINARY 128-pin PQFP Top View CY7C955 AX ATM SONET / SDH TRANSCEIVER 7 CY7C955 102 VSS 101 RSTB 100 CSB 99 VSS 98 RATE[0] 97 RATE[1] 96 TSOC 95 TPRTY 94 TDAT[7] 93 TDAT[6] 92 TDAT[5] 91 TDAT[4] 90 TDAT[3] 89 TDAT[2] 88 TDAT[1] ...
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... The multi-frame indicator, H4, is used to indicate the first ATM cell and may take on values 34h. The remaining bytes, F2, Z3, Z4, and Z5, are not used by the SONET path processing and are set to 00h upon transmission. When operating in STS 1 mode, SPE columns 30 and 59 can be configured as fixed stuff columns. 8 CY7C955 ...
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... D10 D11 Bytes D10D11 D12 Payload Bytes PRELIMINARY D12 F2 Payload 261Bytes Figure 1. STS 3c/STM 1 Framing Format Payload G1 F2 HD1 HD2 HD3 HD4 HEC PAYLOAD Bytes Figure 2. STS 1 Framing Format 9 CY7C955 Payload HD1 HD2 HD3 HD4 HEC PAYLOAD 7C955 3 7C955 4 ...
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... REFCLK x 8 frequency). The standards, however, specify that the RRCLK*8 frequency accuracy be within 20 100 ppm. The wid- er frequency tolerance range of the CY7C955 is an advantage that allows for higher frequency tolerance in bench testing set- ups. ...
Page 11
... VPI/VCI address of 0h. Also, a Header Mask and Header Match register are provided to allow cells with a particular header characteristic in GFC, PTI and CLP to be filtered. The payload of valid cells are descrambled using the polyno- 43 mial x +1. The cell headers are not descrambled since they 11 CY7C955 The coset x ...
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... Carrier Detect Receive Equalization Buffered Transmit Data Fiber or Copper Frequency Media Interface Multiplication & Transmit Buffering CY7C955 ATM SONET/SDH Transceiver (AX) PRELIMINARY ATM DELINEATION SYNC STATE Apparent Multi-Bit Error (Drop Cell) Single Bit Error (Correct Error and Pass Cell) No Errors Detected (Pass Cell) Figure 3 ...
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... PRELIMINARY NOTE [NOTE 1] 1] [NOTE [NOTE D10 Note: 1. B1, B2, Z2, G1, H4, and B3 are variables. Figure 5. Default Values for the Transmitted Section and Line STS 3C/STM 1 Overhead D11 1] [NOTE CY7C955 D12 7C955 7 ...
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... PRELIMINARY NOTE NOTE D10 Figure 6. Default Values for the Transmitted Section and Line STS 1 Overhead D11 D12 1 NOTE 7C955 8 14 CY7C955 ...
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... PRELIMINARY NOTE NOTE NOTE 7C955 9 Figure 7. Default Values for the Transmitted Path Overhead 15 CY7C955 ...
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... Register File Selection Error Monitoring Receive Receive Receive Path Line Section Overhead Overhead Overhead Processor Processor Processor Diagnostic Loopback 16 CY7C955 Transmit TXD± Transmit Section TXC± Clock Overhead TRCLK± Multiplier & Processor Transmit Buffer Rate Selection SONET/SDH Clock ALOS± ...
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... The concatenation indication byte is also inserted (H1* = 93, H2* = FF). Receive Side: H1 and H2 are used to locate the beginning of the SPE valid pointer cannot be found, CY7C955 will indicate a Loss of Pointer State. Path AIS is detected by an all-ones pattern in H1 and H2 bytes. ...
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... CY7C955 Register Map Address Reg 00H Master Reset/Type/Identify Register Reg 01H Master Configuration Register Reg 02H Master Interrupt Register Reg 04H Master Clock Monitor Register Reg 05H Master Control Register Reg 06H Transmit Clock Synthesis Control Register Reg 07H Receive Clock Synthesis Control Register ...
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... Leaving this register puts the AX in power-down mode. 0: Normal mode. 1: Reset / Power Down Mode. TYPE[2:0] These bits differentiate the AX with other Cypress products. ID[3:0] These bits show the revision number of the CY7C955. PRELIMINARY Register NAME 19 CY7C955 READ/WRITE DEFAULT R/W ...
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... RCA is active HIGH. 1: RCA is active LOW. RXDINV This bit controls the interpretation of the differential pair RXD. 0: Logical 1 is represented by RXD+ HIGH and RXD LOW. 1: Logical 0 is represented by RXD+ HIGH and RXD LOW. PRELIMINARY NAME 20 CY7C955 READ/WRITE DEFAULT R/W 1 R/W 1 R/W 1 R/W 0 R/W ...
Page 21
... This is the Receive Section Overhead Processor Interrupt. This bit resets when Reg 02H is being read. This register is a logical OR or all the Receive Section Overhead Processor (RSOP) interrupts or Reg 11H. 1: BIPEI, LOSI, LOFI, or OOFI is HIGH. 0: BIPEI, LOSI, LOFI, and OOFI are all LOW. PRELIMINARY NAME 21 CY7C955 READ/WRITE DEFAULT ...
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... This bit can be read to check for TCLK transitions; when HIGH, this bit stays HIGH until Reg 04H is being read. 1: TRCLK+ has a LOW to HIGH transition since this register was last read. 0: TRCLK+ has no LOW to HIGH transitions since this register was last read. PRELIMINARY NAME 22 CY7C955 READ/WRITE DEFAULT R ...
Page 23
... The setting in Reg 41H can control the payload pointer adjustment operations. 1: The transmit payload pointer is fixed at 522. LLE This bit controls the line loop-back path of the CY7C955; DLE and LLE cannot be both set Normal operation. 1: RXD+ and RXD are connected to TXD+ and TXD internally. ...
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... TRCLK expects a 6.48-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS 3c/STM 1), the transmit PLL will multiply the TRCLK frequency by 24 times. If RATE0 is LOW (51.84 Mbps, STS 1), the transmit PLL will multiply the TRCLK frequency by 8 times to clock the transmitter. PRELIMINARY NAME 24 CY7C955 READ/WRITE DEFAULT R R/W 0 ...
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... RRCLK expects a 6.480-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS 3c/STM 1), the recovered clock is divided down 24 times before comparing with RRCLK. If RATE0 is LOW (51.84 Mbps, STS 1), the recovered clock is divided down 8 times before comparing with RRCLK. PRELIMINARY NAME 25 CY7C955 READ/WRITE DEFAULT R R/W 0 ...
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... The interrupt pin, INTB, will go LOW upon receiving a loss of frame alarm. OOFE This bit controls whether an Out of Frame alarm generates an interrupt. 0: The interrupt pin, INTB, is not affected by the out of frame alarm. 1: The interrupt pin, INTB, will go LOW upon receiving an out of frame alarm. PRELIMINARY NAME 26 CY7C955 READ/WRITE DEFAULT R R/W 0 R/W ...
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... The Receive Section Overhead Processor Loss of Frame state. LOF is declared when OOF has lasted for more than 3 ms. LOFV stays HIGH until the Receive Section Overhead Processor is in frame for more than 3 ms. OOFV This bit shows the Out of Frame (OOF) status of the CY7C955. 0: The Receive Section Overhead Processor is in frame. ...
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... BIP 8 error counter is reset to zero to begin another round of error accumulation. Reading Reg 12H and Reg 13H after the write yields the number of BIP 8 (B1) errors accumulated since the counter was last written to if overflow has not occurred. PRELIMINARY NAME NAME 28 CY7C955 READ/WRITE DEFAULT ...
Page 29
... This bit generates a framing byte error in the transmit data stream. 0: Normal operation. 1: The most significant bit of the section overhead framing byte is converted from other words, F6H becomes H in the first A1 byte of the section overhead. PRELIMINARY NAME NAME 29 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 READ/WRITE DEFAULT R/W ...
Page 30
... This bit is the Line Alarm Indication Signal (LAIS) status register Line AIS detected. 1: Line AIS has been detected. Line AIS is triggered by LOS or LOF. RDIV This bit is the Remote Defect Indication status register remote defect indication (RDI) detected. 1: Remote defect indication (RDI) has been detected. PRELIMINARY NAME 30 CY7C955 READ/WRITE DEFAULT R ...
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... This is the Remote Defect Indication (RDI) interrupt bit. This bit resets when Reg 19H is being read line remote defect indication has been detected since Reg 19H was last read. 1: Line remote defect indication has been detected since Reg 19H was last read. PRELIMINARY NAME 31 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 R/W ...
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... BIP 8/24 error counter is reset to zero to begin another round of error accumulation. Reading Reg 1AH, Reg 1BH, and Reg 1CH after the write yields the number of BIP 8/24 (B2) errors accumulated since the counter was last reset, if overflow has not occurred. PRELIMINARY NAME NAME 32 CY7C955 READ/WRITE DEFAULT ...
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... At that time (1 s after the write operation), these three registers are updated and the internal line FEBE error counter is reset to zero to begin another round of error accumulation. Reading Reg 1DH, Reg 1EH, and Reg 1FH after the write yields the number of line FEBE (Z2) errors accumulated since the counter was last reset, if overflow has not occurred. PRELIMINARY NAME NAME 33 CY7C955 READ/WRITE DEFAULT ...
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... At that time (1 s after the write operation), these three registers are updated and the internal line FEBE error counter are reset to zero to begin another round of error accumulation. Reading Reg 1DH, Reg 1EH, and Reg 1FH after the write yields the number of line FEBE (Z2) errors accumulated since the counter was last reset, if overflow has not occurred. PRELIMINARY NAME NAME 34 CY7C955 READ/WRITE DEFAULT ...
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... BIT POSITION 7 Unused 6 Unused 5 Unused 4 Unused 3 Unused 2 Unused 1 Unused 0 DBIP DBIP This bit generates a continuous line BIP 8/24 (B2) error in the transmit data stream. 0: Normal operation. 1: Insert BIP8/24 (B2) error by inverting the B2 byte. PRELIMINARY NAME NAME 35 CY7C955 READ/WRITE DEFAULT R/W 0 READ/WRITE DEFAULT R/W 0 ...
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... No path alarm indication signal detected. 1: Path alarm indication signal detected. PRDI This bit is the path Far-End Receive Failure (RDI) alarm register path far-end receive failure (RDI) alarm detected. 1: Path far-end receive failure (RDI) alarm detected. PRELIMINARY NAME 36 CY7C955 READ/WRITE DEFAULT ...
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... This is the path Far-End Block Error (FEBE) interrupt bit. This bit resets when Reg 31H is being read path far-end block error detected since Reg 31H was last read. 1: Path far-end block error has been detected since Reg 31H was last read. PRELIMINARY NAME 37 CY7C955 READ/WRITE DEFAULT ...
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... BIP 8 (B3) error will generate an interrupt. FEBEE This bit controls whether line far end block error generates an interrupt by asserting INTB LOW. 0: Line far-end block error will not generate an interrupt. 1: Line far-end block error will generate an interrupt. PRELIMINARY NAME 38 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 R/W 0 R/W ...
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... BIP 8 (B3) error counter is reset to zero to begin another round of error accumulation. Reading Reg 38H and Reg 39H after the write yields the number of BIP 8 (B3) errors accumulated since the counter was last reset, if overflow has not occurred. PRELIMINARY NAME NAME 39 CY7C955 READ/WRITE DEFAULT ...
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... FEBE error counter is reset to zero to begin another round of error accumulation. Reading Reg 3AH and Reg 3BH after the write yields the number of path FEBE (G1) errors accumulated since the counter was last reset, if overflow has not occurred. PRELIMINARY NAME NAME 40 CY7C955 READ/WRITE DEFAULT ...
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... BIP 8 (B3) errors are accumulated and reported in a bit basis. 1: BIP 8 (B3) errors are accumulated and reported in a block basis. Only one BIP 8 error is reported to the upstream path even if more than one path BIP 8 (B3) errors are detected. PRELIMINARY NAME NAME 41 CY7C955 READ/WRITE DEFAULT ...
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... The path BIP 8 (B3) byte is inverted, eight BIP 8 (B3) errors are thus generated per frame PAIS. PAIS This bit generates a path Alarm Indication Signal (AIS) in the transmit data stream. 0: Normal operation. 1: The whole synchronous payload envelope (SPE) together with the H1, H2, and H3 bytes are converted to 1 before scrambling. PRELIMINARY NAME 42 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 ...
Page 43
... This bit can be used to generate a positive pointer movement. This bit has to be first enabled by setting FIXPTR (Reg 05H, bit This bit resets to zero automatically after every write to it. 0: Default state single positive pointer adjustment will be made on the outgoing data stream. This bit will be cleared to zero immediately. PRELIMINARY NAME 43 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 R/W 0 ...
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... H1 and H2 of the transmitted data stream. The value loaded into these 10 bits has to be greater than or equal to zero and smaller than 782. A legal value stored in APTR[9:0] is not loaded into the data stream until PLD or FTPTR is toggled HIGH. PRELIMINARY NAME NAME 44 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 ...
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... Normal operation. With the PRDI bit of G1 only affected by the setting of AUTOPRDI (Reg 01H, Bit 4) and the alarm conditions. 1: The PRDI bit set to 1. G1[2:0] These bits are inserted into the unused bit positions every frame. PRELIMINARY NAME NAME 45 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 R/W 0 R/W ...
Page 46
... This bit is the receive FIFO reset bit. 0: Normal receive FIFO operation. 1: All receive FIFO locations are reset and the receive FIFO will ignore all writes. PRELIMINARY NAME added to the HCS byte before HCS comparison is performed. 46 CY7C955 READ/WRITE DEFAULT R R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 ...
Page 47
... This is the receive FIFO overflow interrupt bit. This bit resets as Reg 51H is being read receive FIFO overflow has occurred since Reg 51H was last read. 1: Receive FIFO overflow has occurred since Reg 51H was last read. PRELIMINARY NAME 47 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 R/W ...
Page 48
... This is the Cell Loss Priority (CLP) register bit. If the PASS bit (Reg 50H, bit 5) is LOW, ATM cells with VPI = 0, VCI = 0,and with other parts of their header matching all the unmasked bits of this register will be dropped. Each bit of this register can be masked bits corresponding bit in Reg 53H. Masked bits are not compared. PRELIMINARY NAME 48 CY7C955 READ/WRITE DEFAULT R/W 0 R/W ...
Page 49
... HCS error counter is reset to zero to begin another round of error accumulation. Reading Reg 54H and Reg–55H after the write yields the number of correctable HCS errors accumulated since the counter was last reset, if overflow has not occurred. PRELIMINARY NAME NAME 49 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 ...
Page 50
... Reading Reg 56H, Reg 57H, and Reg 58H after the write yields the number of cells received since the counter was last reset, if overflow has not occurred. PRELIMINARY NAME NAME 50 CY7C955 READ/WRITE DEFAULT ...
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... Reading Reg 56H, Reg 57H, and Reg 58H after the write yields the number of cells received since the counter was last reset, if overflow has not occurred. PRELIMINARY NAME NAME 51 CY7C955 READ/WRITE DEFAULT ...
Page 52
... HCS error is needed before the 4th cell is accepted. Correction mode is entered immediately after that. 01: 1 cell with no HCS error is needed before the 2nd cell is accepted. Correction mode is entered immediately after that. 00: All cell with no HCS error is accepted. Correction mode is entered immediately after that. PRELIMINARY NAME 52 CY7C955 READ/WRITE DEFAULT R/W 1 R/W 1 R/W ...
Page 53
... This bit is the transmit FIFO reset bit. 0: Normal transmit FIFO operation. 1: All transmit FIFO locations are reset and the transmit FIFO will ignore all writes. PRELIMINARY NAME added to the HCS byte before the ATM cell is inserted into the 53 CY7C955 READ/WRITE DEFAULT R R/W 0 R/W 1 R/W 0 R/W ...
Page 54
... This register contains the octet to be placed in each byte of the transmitted idle cells. When there are no user ATM cells available for transmission, the Transmit ATM Cell Processor generates its own idle cells based on setting in Reg 61H and 62H. Idle cells allow CY7C955 to perform cell rate decoupling. PRELIMINARY ...
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... TCA will go LOW when transmit FIFO is N cells full determined by value in FIFODP[1:0] (Reg 63H, bit 2 3). 1: TCA will stay LOW when transmit FIFO is within 4 bytes from N cells full determined by value in FIFODP[1:0] (Reg 63H, bit 2 3). PRELIMINARY NAME 55 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 ...
Page 56
... Reading Reg 64H, Reg 65H, and Reg 66H after the write yields the number of cell transmitted since the counter was last reset, if overflow has not occurred. TCELL[18:0] should be polled once a second to prevent the register from being saturated. PRELIMINARY NAME NAME 56 CY7C955 READ/WRITE DEFAULT ...
Page 57
... Reading Reg 64H, Reg 65H, and Reg 66H after the write yields the number of cells transmitted since the counter was last reset, if overflow has not occurred. TCELL[18:0] should be polled once a second to prevent the register from being saturated. PRELIMINARY NAME 57 CY7C955 READ/WRITE DEFAULT ...
Page 58
... This register holds the number to be used in the fixed byte columns. 11: FFH is inserted into the fixed byte columns. 10: AAH is inserted into the fixed byte columns. 01: 55H is inserted into the fixed byte columns. 00: 00H is inserted into the fixed byte columns. PRELIMINARY NAME 58 CY7C955 READ/WRITE DEFAULT R/W 0 R/W 0 R/W 0 R/W 0 R/W ...
Page 59
... This is the input output three-state control bit. 0: Normal operation. 1: All I/Os except the data bus are being held at the HIGH impedance state. The CY7C955 read/write is still possible. Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................. – ...
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... TCLK and for all others DATA[0:7] [4] [5] V =0V OUT Rate (51.84 Mbps, STS–1) Rate (155.52 Mbps, STS–3c/ STM–1) RSTB = 0, or RESET (Reg–00H, bit 900 A. OHT 60 CY7C955 Min. Max. Unit [ 2.5 200 2500 mV 500 –200 [2] [2] [2] – ...
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... HLA t Address Latch Enable Pulse Width PL t Address Latch Enable to Write Set-Up SLW PRELIMINARY (b) PECL AC Test Load V IHE 2.0V 1.0V 20% V ILE 7C955-13 (d) PECL Input Test Waveform Description 61 CY7C955 Max. Unit – < (Includes fixture and probe capacitance) 7C955-12 V IHE 80% 80% ...
Page 62
... TWRENB / TDAT[7:0] / TXPRTY / TSOC Stable to TFCLK HIGH Set-Up STC Notes: 8. Not Tested. 9. See description on Receive Clock Recovery (RCR) page 10 PRELIMINARY Description 19.44 MHz or 6.48 MHz (RBYP = 0) [ BYP = 1 BYP 19.44 MHz or 6.48 MHz (TBYP = 0) 62 CY7C955 Min. Max. Unit 250 250 ppm 2 ...
Page 63
... HTG t TCLK High to TCP Valid Delay DTP Switching Waveforms Microprocessor Interface Read Cycle A[7:0] ALE (RDB + CSB) D[7:0] INTB PRELIMINARY Description VALID ADDRESS t SAL t HLA SLR t SAR t SRD 63 CY7C955 Min. Max. Unit – HRA t HRL t HRD VALID DATA t SRI 7C955– ...
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... Microprocessor Interface Write Cycle A[7:0] ALE (WRB + CSB) D[7:0] Receive Side Line Interface Timing RXD± RRCLK± PRELIMINARY VALID ADDRESS t SAL t HLA SLW t t SAW t SDC 64 CY7C955 t HWA t HWL PW t HWD t SDW VALID DATA 7C955–16 t HCD 7C955–17 ...
Page 65
... Switching Waveforms (continued) Receiver Alarm Interface Timing RCLK RALM / RFP Transmit Side Line Interface Timing TCLK TFPO TXC± TXD± PRELIMINARY t DCR t DCT t DCD 65 CY7C955 7C955–18 7C955–19 ...
Page 66
... Switching Waveforms (continued) Utopia Interface (Receive Side) Timing [TSEN = 0] RFCLK RRDENB RDAT[7:0] / RCA / RSOC / RXPRTY PRELIMINARY t SRC t HCR t DCD 66 CY7C955 7C955–20 ...
Page 67
... Switching Waveforms (continued) Utopia Interface (Receive Side) Timing [TSEN=1] RFCLK RRDENB RCA RDAT[7:0] / RSOC / RXPRTY GFC Interface (Receive Side) Timing RCLK RGFC / RCP PRELIMINARY t DCA t DCD VALID RDAT[7:0] / RSOC / RXPRTY t DCG 67 CY7C955 t SRC t HCR t DCT 7C955–21 7C955–22 ...
Page 68
... Switching Waveforms (continued) Utopia Interface (Transmit Side) Timing RCLK RRDENB RCA GFC Interface (TransmitSide)Timing TCLK TGFC TCP PRELIMINARY t t STC HCT t DTT t t SGT HTG t DTP 68 CY7C955 7C955–23 7C955–24 ...
Page 69
... If this clock is stopped, the line side interface will still be able to transmit the cells already stored into the FIFO. After that, idle cells will be transmitted. P46 H3 P44 P45 Figure 8. Transmit FIFO 69 CY7C955 X P47 P48 H1 X TCA LEVEL 0 =1 ...
Page 70
... The RXPTYP (Reg–50, bit 6) can be set to make the receive side Utopia interface produce odd or even parity RXPRTY out- puts. RSOC RSOC will go HIGH when RDAT[7:0] contains the first header byte of an ATM cell. H2 P43 P44 P45 Figure 9. Receive FIFO 70 CY7C955 H1 P46 P47 P48 READ IGNORED RCALEVEL0= 1 ...
Page 71
... RGFC pin. GFC[3] can be present for as long RCLK cycles on the RGFC pin, and so RCP can also be HIGH for anywhere between RCLK cycles. GFC[3] GFC[2] GFC[1] Figure 10. Transmit GFC Serial Link GFC[2] GFC[1] GFC[0] CELL N CELL N CELL N GFC[0] CELL N Figure 11. Receive GFC Serial Link 71 CY7C955 GFC[0] X ...
Page 72
... HIGH to enable loop timing mode. In loop timing mode, The clock recovered from the received data stream is being used to synchronize the transmit datastream. If that clock is lost, RRCLK x 8 will be used as the clock refer- ence. The clocking architecture of the CY7C955 is shown in Figure 14. Stratum or free-run reference Input Data TRCLK± ...
Page 73
... If the trace is long, follow common transmission line termination practices. Figure 18 shows a TTL connection. The 0.01 F AC-coupling /2. Notice that CC capacitor allows the CY7C955 inputs to self-bias itself to V /2. This connection scheme is not suitable for the ALOS CC input because the signal is close to static. ...
Page 74
... PECL Output 330 Figure 16. Differential PECL Termination (Low Power) CMOS Output Figure 17. CMOS Connection 74 CY7C955 ALOS+ / TRCLK+ / RRCLK+ / RXD+ CY7C955 ALOS– / TRCLK– / RRCLK– / RXD– ALOS+ / TRCLK+ / RRCLK+ / RXD+ CY7C955 ALOS– / TRCLK– / RRCLK– / RXD– ...
Page 75
... Figure 18. TTL Connection ALOS+ ALOS– 330 provide the damping factor needed to meet the jitter ceiling de- fined in GR-253. Figure 14 describes how to connect the ca- pacitor across the LF and LFO pins of the CY7C955. The LF+ pin left unconnected. 16V or higher ±10% or better X7R or better Non-polar or Bipolar ...
Page 76
... Capacitance: 0.47 F Dielectric: X7R Tolerance: ±10% Phase Detector Figure 20. Phase-Locked Loop Capacitor Placement Ordering Information Package Ordering Code Name CY7C955-NC N128 CY7C955-NI N128 Document #: 38-00417-D PRELIMINARY 16V or higher ±10% or better X7R or better Non-polar or Bipolar 1206 or 1210 (0805 is not available commercially yet) ...
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... Package Diagram PRELIMINARY 128-Lead Plastic Quad Flatpack 77 CY7C955 ...
Page 78
... ADDENDUM - Design Considerations for the CY7C955 This memo outlines current design considerations for the CY7C955 - ATM PHY in reference to the ATM Forum UTOPIA Level 1 specification. Receive FIFO Reset The Receive four-cell FIFO is reset by programming register 0x50(RACP)[ logic '1'. Under this condition the CY7C955 RCA output is not deassert- ed immediately and the RDATA[7:0] output is not 0x00 ...