CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 52

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

REG
7
6
5
4
3
2
1
0
RGFCE[3:0]
This is the Receive Generic Flow Control Enable register. Each bit is logical ANDed with its corresponding bit in the ATM cell
header. RGFCE[3] corresponds to the most significant bit of the GFC header. If RGFC[x] is set LOW, then bit x of the serial
RGFC output (pin 59) will appear LOW.
FSEN
This is the fix stuff expectation bit. This command only affects STS 1 frames.
0:
1:
RCALEVEL0
This is the receive cell available (RCA) pin empty definition control register.
0:
1:
HCSFTR[1:0]
This is the HCS cell acceptance threshold register. These bits control how many consecutive error-free cells are needed for the
Receive ATM cell processor to convert from detection mode to correction mode.
11:
10:
01:
00:
BIT POSITION
No fix stuff bytes are expected in the STS 1 payload.
Fix stuff bytes are expected in Column 30 and 59 of the received STS 1 frame.
RCA is an active LOW indication for the receive FIFO being 4 bytes from empty.
RCA is an active LOW indication for the receive FIFO being empty.
7 cells with no HCS error is needed before the 8th cell is accepted. Correction mode is entered immediately after that.
3 cells with no HCS error is needed before the 4th cell is accepted. Correction mode is entered immediately after that.
1 cell with no HCS error is needed before the 2nd cell is accepted. Correction mode is entered immediately after that.
All cell with no HCS error is accepted. Correction mode is entered immediately after that.
59H
Receive ATM Cell Processor Receive Configuration Register
RGFCE[3]
RGFCE[2]
RGFCE[1]
RGFCE[0]
FSEN
RCALEVEL0
HCSFTR[1]
HCSFTR[0]
PRELIMINARY
NAME
52
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
READ/WRITE
1
1
1
1
1
1
0
0
CY7C955
DEFAULT