CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 24

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

REG
7
6
5
4
3
2
1
0
TROOLV
This bit is the Transmit Reference Out Of Lock Status register.
0:
1:
TROOLE
This bit is the Transmit Reference Out Of Lock Interrupt Enable register.
0:
1:
TREFSEL
This bit is the Transmit Reference Select. This bit is ignored in transmit bypass mode (TBYP = 1).
0:
1:
BIT POSITION
The divided-down synthesized transmit clock is within 2930 ppm of TRCLK or RRCLK (in loop timing mode).
The divided-down synthesized transmit clock is not within 2930 ppm of TRCLK or RRCLK (in loop timing mode).
INTB, the interrupt pin, will not be affected by transmit out of lock.
INTB, the interrupt pin, will pull LOW when there is a state change of TROOLV.
TRCLK expects a 19.44-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS 3c/STM 1), the transmit PLL will
multiply the TRCLK frequency by 8 times. If RATE0 is LOW (51.84 Mbps, STS 1), the transmit PLL will multiply the
TRCLK frequency by 8/3 times to clock the transmitter.
TRCLK expects a 6.48-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS 3c/STM 1), the transmit PLL will
multiply the TRCLK frequency by 24 times. If RATE0 is LOW (51.84 Mbps, STS 1), the transmit PLL will multiply the
TRCLK frequency by 8 times to clock the transmitter.
06H
Unused
Unused
Unused
Unused
TROOLV
Unused
TROOLE
TREFSEL
Transmit Clock Synthesis Control Register
PRELIMINARY
NAME
24
R
R/W
R/W
READ/WRITE
0
0
CY7C955
DEFAULT