CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 25

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

REG
7
6
5
4
3
2
1
0
RROOLV
This bit is the Receive Reference Out Of Lock Status register.
0:
1:
RROOLE
This bit is the Receive Reference Out Of Lock Interrupt Enable register.
0:
1:
RREFSEL
This bit is the Receiver Reference Select. This bit is ignored in receiver bypass mode (RBYP = 1).
0:
1:
BIT POSITION
The divided-down recovered clock is within 2930 ppm of RRCLK, and there is at least one transition on RXD during
The divided-down recovered clock is not within 2930 ppm of RRCLK, or there are no transitions on RXD within the last
80 bit-periods.
INTB, the interrupt pin, will not be affected by receiver out of lock.
INTB, the interrupt pin, will go LOW when there is a state change of RROOLV.
RRCLK expects a 19.44-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS 3c/STM 1), the recovered clock
is divided down 8 times before comparing with RRCLK. If RATE0 is LOW (51.84 Mbps, STS 1), the recovered clock is
divided down 3/8 times before comparing with RRCLK.
RRCLK expects a 6.480-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS 3c/STM 1), the recovered clock
is divided down 24 times before comparing with RRCLK. If RATE0 is LOW (51.84 Mbps, STS 1), the recovered clock is
divided down 8 times before comparing with RRCLK.
the last 80 bit-periods.
07H
Receive Clock Synthesis Control Register
Unused
Unused
Unused
Unused
RROOLV
Unused
RROOLE
RREFSEL
PRELIMINARY
NAME
25
R
R/W
R/W
READ/WRITE
0
0
CY7C955
DEFAULT