CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 46

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

REG
7
6
5
4
3
2
1
0
OOCDV
This bit is the cell delineation status register.
0:
1:
RXPTYP
This bit controls whether odd or even parity is used for RXPRTY.
0:
1:
PASS
This bit controls whether cells with VPI = 0 and VCI = 0 are dropped.
0:
1:
DISCOR
This bit controls whether header error (HCS) correction is performed.
0:
1:
HCSPASS
This bit controls whether cells with HCS error are dropped.
0:
1:
HCSADD
This bit controls whether the coset polynomial x
0:
1:
DDSCR
This bit controls whether cell payload descrambling is performed.
0:
1:
FIFORST
This bit is the receive FIFO reset bit.
0:
1:
BIT POSITION
This indicates that the cell delineation state machine is in the ‘SYNC’ state and ATM cells are passing though to the
receive FIFO.
This indicates that the cell delineation state machine is in the ‘PRESYNC’ or ‘HUNT’ state.
Odd parity is generated for RDAT[7:0].
Even parity is generated for RDAT[7:0].
All cells with VPI = 0, VCI = 0 and header matching all the unmasked bits of Reg 52H are dropped.
No cell filtering is performed.
Header error correction is performed. Single bit-errors detected in the header are corrected automatically.
Header error correction is not performed. Any HCS error detected is considered uncorrectable.
All cells with an uncorrectable HCS error are dropped.
No cells are dropped if the cell delineation state machine is in SYNC state.
No coset polynomial is added.
The coset polynomial x
Cell payload descrambling is performed.
Cell payload descrambling is not performed.
Normal receive FIFO operation.
All receive FIFO locations are reset and the receive FIFO will ignore all writes.
50H
Receive ATM Cell Processor Control and Status Register
OOCDV
RXPTYP
PASS
DISCOR
HCSPASS
HCSADD
DDSCR
FIFORST
6
+x
4
+x
2
+1 is added to the HCS byte.
PRELIMINARY
6
+x
NAME
4
+x
2
+1 is added to the HCS byte before HCS comparison is performed.
46
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
READ/WRITE
0
0
0
0
1
0
0
CY7C955
DEFAULT