L80223 LSI, L80223 Datasheet - Page 132

• Manufacturer Part Number: L80223
• Manufacturer: LSI

Specifications of L80223

• Lead Free Status / RoHS Status: Not Compliant

Figure A.4
loh
A.6.3 MII Disable
A-10
I
I
I
I
1
2
3
4
I – V
, – V
, – V
, – V
, – V
1
2
3
4
I (mA)
43
20
4
Rol
4
MII Output Driver Characteristics
min
V (Volts)
= 40 ohm
1.10
2.40
0.40
3.05
Setting the MII disable bit (MII_DIS) in the MI serial port Control register
places the MII outputs in the high-impedance state and the disables the
MII inputs. When this bit is set to the disable state, the TP outputs are
also disabled and transmission is inhibited. The default value of this bit
when the device powers up or is reset is dependent on the physical
device address. If the device address latched into MDA[3:0]n at reset is
0b1111, it is assumed that the device is being used in applications where
there maybe more than one device sharing the MII bus, such as in the
use of external PHYs or adapter cards. In this case, the device powers
up with the MII interface disabled. If the device address latched into
MDA[3:0]n at reset is not 0b1111, it is assumed that the device is being
used in application where it is the only device on the MII bus, such as in
the use of hubs, so the device powers up with the MII interface enabled.
Application Information
V
1
I
1
V
2
V
I
2
DD
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Voh
Vol
I
3
V
3
I
4
V
4
Rol
min
= 40 ohm
lol