L80223 LSI, L80223 Datasheet - Page 86

• Manufacturer Part Number: L80223
• Manufacturer: LSI

Specifications of L80223

• Lead Free Status / RoHS Status: Not Compliant

5.3 Frame Structure
Figure 5.2
5-4
IDLE
ST[1:0]
MI Serial Frame Structure
READ
The structure of the serial port frame is shown in
diagram is shown in
of 32 bits (or 144 bits if multiple register access is enabled and
REGAD[4:0] = 0b11111), exclusive of idle. The first 16 bits of the serial
port cycle are always write bits and are used for control and addressing.
The last 16 bits are data that is written to or read from a data register.
The first two bits in
must be written as a 0b01 for the serial port cycle to continue. The next
two bits are the READ and WRITE bits, which determine whether the
registers are being read or written. The next five bits are the PHY device
address bits (PHYAD[4:0]), and they must match the inverted values
latched from the MDA[4:0]n pins during the power on reset time for
access to continue.
The next five bits are register address select (REGAD[4:0]) bits, which
select one of the eight registers for access. The next two bits are
turnaround (TA) bits, which are not actual register bits but provide the
device extra time to switch the MDIO pin function from a write pin to a
read pin, if necessary. The final 16 bits of the MI serial port cycle are
written to or read from the specific data register that the register address
bits (REGAD[4:0]) designate.
IDLE
ST[1:0]
READ
Management Interface
WRITE
Idle Pattern
These bits are an idle pattern. The device does not
initiate an MI cycle until it detects an idle pattern of at
least 32 consecutive 1s.
Start Bits
When ST[1:0] = 01, a MI serial port access cycle starts.
Read Select
When the READ bit is 1, it designates a read cycle.
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
PHYAD[4:0]
Figure 5.2
Figure
5.1. Each serial port access cycle consists
Figure 5.2
and
REGAD[4:0]
Figure 5.1
shows the MI frame structure.
are start bits (ST[1:0]) and
Figure 5.2
TA[1:0]
and a timing
D[15:0]
W
W
W