L80223 LSI, L80223 Datasheet - Page 59

• Manufacturer Part Number: L80223
• Manufacturer: LSI

Specifications of L80223

• Lead Free Status / RoHS Status: Not Compliant

3.2 Controller Interface Signals (MII)
TPI+
TPI-
CRS
OSCIN
RX_CLK
RXD[3:0]
RX_DV
RX_EN
RX_ER
Controller Interface Signals (MII)
Twisted-Pair Receive Input (Positive)
The TPI+ pin functions as the positive signal in the
twisted-pair input.
Twisted-Pair Receive Input (Negative)
The TPI- pin functions as the negative signal in the
twisted-pair input.
Carrier Sense Output
The CRS output is asserted HIGH when valid data is
detected on the receive TP inputs. CRS is clocked out on
the falling edge of RX_CLK.
Clock Oscillator Input
There must be either a 25 MHz crystal between this pin
and GND or a 25 MHz clock applied to this pin. TX_CLK
output is generated from this input.
Receive Clock Output
Receive data on RXD, RX_DV, and RX_ER is clocked out
to an external controller on the falling edge of RX_CLK.
Receive Data Output
RXD[3:0] contain receive nibble data from the TP input,
and they are clocked out on the falling edge of RX_CLK.
Receive Data Valid Output
RX_DV is asserted HIGH when valid decoded data is
present on the RXD outputs. RX_DV is clocked out on the
falling edge of RX_CLK.
Receive Enable Input
When RX_EN is HIGH, all of the receive outputs
(RX_CLK, RXD[3:0], RX_DV, RX_ER, COL) are enabled.
When RX_EN is LOW, the outputs are in a high-imped-
ance state.
Receive Error Output
RX_ER is asserted HIGH when a coding error or other
specified errors are detected on the receive twisted-pair
inputs. The signal is clocked out on the falling edge of
RX_CLK.
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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