L80223 LSI, L80223 Datasheet - Page 85

• Manufacturer Part Number: L80223
• Manufacturer: LSI

Specifications of L80223

• Lead Free Status / RoHS Status: Not Compliant

Figure 5.1
WRITE Cycle
READ Cycle
MDIO
MDIO
Note: ST = start bits, OP = operation bits (read or write), PHAD = PHY address, REGAD = register address, TA = turnaround bits
MDC
MDC
For more detailed information on the timing related to t
MI Serial Port Frame Timing Diagram
0
0
0
0
ST
ST
1
1
1
1
PHY clocks in data on rising edges of MDC with
t
s
0
1
2
2
= 10 ns minimum, and t
OP
OP
3
3
0
1
P4
P4
4
4
PHY clocks in data on rising edges of MDC with t
P3
P3
5
5
PHYAD
PHYAD
WRITE Bits
P2
P2
6
6
P1
P1
7
7
P0
P0
h
8
8
= 10 ns minimum
R4
R4
9
9
10
10
R3
R3
REGAD
REGAD
11
11
R2
R2
12
12
R1
R1
s,
13
13
t
R0
R0
h, and
14
14
Z 0
1
WRITE Bits
TA
TA
t
d,
15
15
0
D15 D14 D13 D12 D11
please see Chapter 6, “Specifications.”
16
16
D15 D14 D13 D12 D11
s
= 10 ns minimum and t
PHY clocks out data on rising edges of MDC with
17
17
18
18
19
19
20
20
D10 D9
t
d
= 20 ns maximum
21
21
D10 D9
READ Bits
22
22
D8
h
= 10 ns minimum
23
23
DATA
DATA
D8
D7
24
24
D7
D6
25
25
D6
D5
26
26
D5
D4
27
D4
27
D3
D3
28
28
D2
D2
29
29
D1
30
D1 D0
30
D0
31
31