L80223 LSI, L80223 Datasheet - Page 49

• Manufacturer Part Number: L80223
• Manufacturer: LSI

Specifications of L80223

• Lead Free Status / RoHS Status: Not Compliant

2.4.2 10 Mbits/s
2.5 End of Packet
The 4B5B decoder detects the receive pattern. To do this, the decoder
examines groups of 10 consecutive code bits (two 5B words) from the
descrambler. Between packets, the receiver detects the idle pattern
(5B /I/ symbols). When in the idle state, the device deasserts the CRS
and RX_DV pins.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver consist of the /J/K/ symbols, the start of packet is detected, data
reception begins, and /5/5/ symbols are substituted in place of the /J/K/
symbols.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver are a pattern that is neither /I/I/ nor /J/K/ symbols, but contain
at least two noncontiguous zeros, activity is detected but the start of
packet is considered to be faulty and a False Carrier Indication (also
referred to as bad SSD) is signaled to the controller interface.
When False Carrier is detected, CRS is asserted, RX_ER is asserted,
RX_DV remains deasserted, and the RXD[3:0] output state is 0b1110
while RX_ER is asserted.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver consist of a pattern that is neither /I/I/ nor /J/K/ symbols but does
not contain at least two noncontiguous zeros, the data is ignored and the
receiver stays in the idle state.
Because the idle period in 10 Mbits/s mode is defined to be when there
is no valid data on the TP inputs, the start of packet for 10 Mbits/s mode
is detected when the TP squelch circuit detects valid data. When the
start of packet is detected, CRS is asserted as described in
2.3.2, “Controller Interface,” page
Mbits/s),” page 2-20
This section describes end of packet operation for both the 100 Mbits/s
and 10 Mbits/s modes.
End of Packet
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
for details on the squelch algorithm.
2-9. See
Section 2.3.8.4, “Squelch (10
Section
2-31