L80223 LSI, L80223 Datasheet - Page 134

• Manufacturer Part Number: L80223
• Manufacturer: LSI

Specifications of L80223

• Lead Free Status / RoHS Status: Not Compliant

A.8 Serial Port
A.8.1 Serial Port Addressing
A-12
clock from the repeater core. This requires that transmit data be clocked
in on edges of an input clock. The OSCIN input clock is available for
clocking in data on TXD. Notice from the timing diagrams that OSCIN
generates TX_CLK, and TXD data is clocked in on TX_CLK edges. This
means that TXD data is also clocked in on OSCIN edges. Thus, an
external clock driving the OSCIN input can also be used as the clock for
TXD.
The L80227 uses an MI serial port to access the device registers. Any
external device that has a IEEE 802.3 compliant MI interface can connect
directly to the L80227 without any glue logic, as shown in
through
As described earlier, the MI serial port consists of six signals: MDC,
MDIO, and MDA[3:0]n. However, only two signals, MDC and MDIO, are
needed to shift data in and out. MDA[3:0]n are not needed, but are
provided for convenience only.
Note that the MDA[3:0]n addresses are inverted inside the L80227 before
going to the MI serial port block. This means that the MDAn[3:0] pins
would have to be pin strapped to 0b1111 externally to successfully match
the MI physical address of 0b00000 on the PHYAD[4:0] bits internally.
The MSB of the address is internally tied to zero.
Tying the MDA[3:0]n pins to the desired value selects the device address
for the MI serial port. MDA[3:0]n share the same pins as the LED
outputs, respectively, as shown in
output drivers are 3-stated for an interval called the power-on reset time.
During the power-on reset interval, the value on these pins is latched into
the device, inverted, and used as the MI serial port address. The
PLED[5:2]n outputs are open-drain with a pullup resistor and can drive
LEDs tied to V
pulldown driver transistors with a pullup resistor, so the PLED[1:0]n
outputs can drive LEDs tied to either V
Application Information
Figure
DD
A.3.
. The PLED[1:0]n outputs have both pullup and
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure
DD
A.5a. At powerup or reset, the
or GND.
Figure A.1