PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 207

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.1.5
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (F
When Timer1 is clocked by F
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
TABLE 24-2:
 2011 Microchip Technology Inc.
APFCON0
CCP1CON
CCPR1L
CCPR1H
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CCP2CON
CCPR2L
CCPR2H
CCP3CON
CCPR3L
CCPR3H
CCP4CON
CCPR4L
CCPR4H
INTCON
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TRISB
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode.
Name
*
Page provides register information.
CAPTURE DURING SLEEP
Capture/Compare/PWM Register Low Byte (LSB)
Capture/Compare/PWM Register High Byte (MSB)
Capture/Compare/PWM Register Low Byte (LSB)
Capture/Compare/PWM Register High Byte (MSB)
Capture/Compare/PWM Register Low Byte (LSB)
Capture/Compare/PWM Register High Byte (MSB)
Capture/Compare/PWM Register Low Byte (LSB)
Capture/Compare/PWM Register High Byte (MSB)
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
RXDTSEL SDO1SEL
TMR1GIE
TMR1GIF
TMR1GE
C1INTP
C2INTP
TRISA7
TRISB7
OSFIE
OSFIF
C1ON
C2ON
Bit 7
GIE
TMR1CS<1:0>
—
—
—
—
OSC
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
P1M<1:0>
P2M<1:0>
/4), or by an external clock source.
T1GPOL
C1INTN
C2INTN
TRISA6
TRISB6
C1OUT
C2OUT
PEIE
ADIE
C2IE
ADIF
Bit 6
C2IF
—
—
—
—
OSC
/4, Timer1 will not
SS1SEL
TMR0IE
CCP4IE
CCP4IF
TRISA5
TRISB5
T1GTM
C1OE
C2OE
RCIE
RCIF
C1IE
Bit 5
C1IF
T1CKPS<1:0>
C1PCH<1:0>
C2PCH<1:0>
DC1B<1:0>
DC2B<1:0>
DC3B<1:0>
DC4B<1:0>
T1GSPM
P2BSEL
CCP3IE
CCP3IF
TRISA4
TRISB4
C1POL
C2POL
INTE
EEIE
Bit 4
TXIE
TXIF
EEIF
Preliminary
T1GGO/DONE
T1OSCEN
CCP2SEL
TMR6IE
SSP1IE
TMR6IF
TRISA3
TRISB3
BCL1IE
SSP1IF
BCL1IF
IOCE
Bit 3
24.1.6
This module incorporates I/O pins that can be moved to
other locations with the use of the Alternate Pin Func-
tion registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default loca-
tions are upon a Reset, see
Pin Function”
—
—
—
—
P1DSEL
T1SYNC
T1GVAL
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISB2
C1SP
C2SP
ALTERNATE PIN LOCATIONS
CCP4M<3:0)>
Bit 2
CCP1M<3:0>
CCP2M<3:0>
CCP3M<3:0>
—
—
—
—
—
—
for more information.
PIC16(L)F1847
P1CSEL
TMR2IE
TMR4IE
TMR2IF
TMR4IF
TRISA1
TRISB1
C1HYS
C2HYS
INTF
Bit 1
—
—
—
C1NCH<1:0>
C2NCH<1:0>
T1GSS<1:0>
Section 12.1 “Alternate
CCP1SEL
TMR1ON
C1SYNC
C2SYNC
TMR1IE
CCP2IE
TMR1IF
CCP2IF
TRISA0
TRISB0
IOCF
Bit 0
DS41453A-page 207
—
—
Register
on Page
206*
206*
179*
179*
120
228
172
173
173
173
228
228
228
228
228
228
228
228
228
187
188
122
127
89
90
91
92
94
95
96