PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 246

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1847
25.4
All MSSPx I
shifted out MSb first. Six SFR registers and 2 interrupt
flags interface the module with the PIC
troller and user software. Two pins, SDAx and SCLx,
are exercised by the module to communicate with
other external I
25.4.1 BYTE FORMAT
All communication in I
byte is sent from a master to a slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the 8th
falling edge of the SCLx line, the device outputting
data on the SDAx changes that pin to an input and
reads in an Acknowledge value on the next clock
pulse.
The clock signal, SCLx, is provided by the master.
Data is valid to change while the SCLx signal is low,
and sampled on the rising edge of the clock. Changes
on the SDAx line while the SCLx line is high define
special conditions on the bus, explained below.
25.4.2 DEFINITION OF I
There is language and terminology in the description
of I
I
used in the rest of this document without explana-
tion.
specification.
25.4.3 SDAX AND SCLX PINS
Selection of any I
forces the SCLx and SDAx pins to be open-drain.
These pins should be set by the user to inputs by set-
ting the appropriate TRIS bits.
25.4.4 SDAX HOLD TIME
The hold time of the SDAx pin is selected by the
SDAHT bit of the SSPxCON3 register. Hold time is the
time SDAx is held valid after the falling edge of SCLx.
Setting the SDAHT bit selects a longer 300 ns mini-
mum hold time and may help on buses with large
capacitance.
DS41453A-page 246
2
C. That word usage is defined below and may be
Note: Data is tied to output zero when an I
2
C communication that have definitions specific to
This table was adapted from the Phillips I
I
2
mode is enabled.
C
2
Mode Operation
C communication is byte oriented and
2
C devices.
2
C mode with the SSPEN bit set,
2
C is done in 9-bit segments. A
2
C TERMINOLOGY
®
microcon-
Preliminary
2
2
C
C
TABLE 25-2:
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization Procedure to synchronize the
Idle
Active
Addressed
Slave
Matching
Address
Write Request
Read Request
Clock Stretching When a device on the bus hold
Bus Collision
TERM
I
2
The device which shifts data in
Master sends an address byte with
The device which shifts data out
onto the bus.
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
The device addressed by the mas-
ter.
A bus with more than one device
that can initiate data transfers.
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
clocks of two or more devices on
the bus.
No master is controlling the bus,
and both SDAx and SCLx lines are
high.
Any time one or more master
devices are controlling the bus.
Slave device that has received a
matching address and is actively
being clocked by a master.
Address byte that is clocked into a
slave that matches the value
stored in SSPxADD.
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
SCLx low to stall communication.
Any time the SDAx line is sampled
low by the module while it is out-
putting and expected high state.
C BUS TERMS
 2011 Microchip Technology Inc.
Description