PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 312

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1847
FIGURE 26-12:
TABLE 26-8:
DS41453A-page 314
APFCON0
APFCON1
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TRISB
TXSTA
Legend:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
SREN bit
CREN bit
bit SREN
RCIF bit
Name
RCREG
RX/DT
Write to
Read
pin
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
Page provides register information.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
RXDTSEL
TMR1GIE
TMR1GIF
ABDOVF
TRISB7
SPEN
CSRC
Bit 7
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
—
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
SDO1SEL
TRISB6
RCIDL
bit 0
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
—
bit 1
SS1SEL
TMR0IE
TRISB5
SREN
TXEN
RCIE
RCIF
Bit 5
—
—
EUSART Receive Data Register
bit 2
P2BSEL
TRISB4
Preliminary
CREN
SYNC
SCKP
Bit 4
INTE
TXIE
TXIF
—
BRG<15:8>
BRG<7:0>
bit 3
CCP2SEL
SSP1IE
ADDEN
TRISB3
SSP1IF
SENDB
BRG16
IOCE
Bit 3
—
bit 4
P1DSEL
TMR0IF
CCP1IE
CCP1IF
TRISB2
BRGH
FERR
Bit 2
—
—
bit 5
P1CSEL
TMR2IE
TMR2IF
TRISB1
OERR
TRMT
WUE
Bit 1
INTF
 2011 Microchip Technology Inc.
bit 6
—
CCP1SEL
TXCKSEL
TMR1IE
TMR1IF
TRISB0
ABDEN
bit 7
RX9D
TX9D
IOCF
Bit 0
Register
on Page
294*
301*
301*
120
120
300
299
127
298
89
90
94
‘0’