PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 32

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1847
TABLE 3-8:
DS41453A-page 32
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
Legend:
Note
Address
Bank 3
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
ANSELB
—
—
—
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
—
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
BAUDCON
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
These registers can be addressed from any bank.
Name
Shaded locations are unimplemented, read as ‘0’.
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
Unimplemented
Unimplemented
Unimplemented
EEPROM / Program Memory Address Register Low Byte
EEPROM / Program Memory Read Data Register Low Byte
EEPROM control register 2
Unimplemented
Unimplemented
USART Receive Data Register
USART Transmit Data Register
Baud Rate Generator Data Register Low
Baud Rate Generator Data Register High
ABDOVF
EEPGD
ANSB7
CSRC
SPEN
Bit 7
GIE
—
—
—
—
—
—
Write Buffer for the upper 7 bits of the Program Counter
EEPROM / Program Memory Address Register High Byte
ANSB6
RCIDL
CFGS
Bit 6
PEIE
RX9
TX9
—
—
—
—
EEPROM / Program Memory Read Data Register High Byte
TMR0IE
ANSB5
LWLO
SREN
TXEN
Bit 5
—
—
—
—
Preliminary
ANSA4
ANSB4
CREN
SYNC
SCKP
BSR4
FREE
INTE
Bit 4
TO
WRERR
ADDEN
SENDB
ANSA3
ANSB3
BRG16
BSR3
IOCE
Bit 3
PD
TMR0IF
ANSA2
ANSB2
WREN
BRGH
FERR
BSR2
Bit 2
—
Z
ANSA1
ANSB1
OERR
TRMT
 2011 Microchip Technology Inc.
BSR1
INTF
WUE
Bit 1
WR
DC
ABDEN
ANSA0
BSR0
RX9D
TX9D
IOCF
Bit 0
RD
—
C
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
---1 1111 ---1 1111
1111 111- 1111 111-
0000 0000 0000 0000
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
0000 x000 0000 q000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000x
0000 0010 0000 0010
01-0 0-00 01-0 0-00
POR, BOR
Value on:
—
—
—
—
—
Value on
all other
Resets
—
—
—
—
—