PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 93

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.5.5
The PIE4 register contains the interrupt enable bits, as
shown in
REGISTER 8-5:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
bit 0
U-0
—
Register
PIE4 REGISTER
Unimplemented: Read as ‘0’
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1 = Enables the MSSP2 Bus Collision Interrupt
0 = Disables the MSSP2 Bus Collision Interrupt
SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit
1 = Enables the MSSP2 interrupt
0 = Disables the MSSP2 interrupt
8-5.
U-0
—
PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U-0
—
Note 1: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
PIC16(L)F1847
—
R/W-0/0
BCL2IE
DS41453A-page 93
R/W-0/0
SSP2IE
bit 0