SAA7103HV4 NXP Semiconductors, SAA7103HV4 Datasheet - Page 10

• Manufacturer Part Number: SAA7103HV4
• Manufacturer: NXP Semiconductors

Specifications of SAA7103HV4

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
SAA7102_SAA7103_4
Product data sheet
7.4 Cursor insertion
A 32 dots × 32 dots cursor can be overlaid as an option; the bit map of the cursor can be
uploaded by an I
the PD port. In the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel)
are expected immediately following the last RGB LUT data in the line preceding the first
active line.
The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these
bits depends on the CMODE I
that the input pixels are passed through, the ‘cursor colors’ can be programmed in
separate registers.
The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first
pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the
column, followed by the row; index 0,0 is the upper left corner.
Table 6:
For each direction, there are 2 registers controlling the position of the cursor, one controls
the position of the ‘hot spot’, the other register controls the insertion position. The hot spot
is the ‘tip’ of the pointer arrow. It can have any position in the bit map. The actual position
registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner.
While it is not possible to move the hot spot beyond the left respectively upper screen
border this is perfectly legal for the right respectively lower border. It should be noted that
the cursor position is described relative to the input resolution.
Table 7:
Byte
0
1
2
...
6
7
...
254
255
D1
7
pixel n + 3
Layout of a byte in the cursor bit map
Cursor bit map
D0
6
row 0 column 3
row 0 column 7
row 0 column 11
...
row 0 column 27
row 0 column 31
...
row 31 column 27
row 31 column 31
2
C-bus write access to specific registers or in the pixel data input through
7
Rev. 04 — 18 January 2006
D1
5
pixel n + 2
6
2
C-bus register as described in
row 0 column 2
row 0 column 6
row 0 column 10
...
row 0 column 26
row 0 column 30
...
row 31 column 26
row 31 column 30
D0
5
4
4
SAA7102; SAA7103
D1
3
pixel n + 1
row 0 column 1
row 0 column 5
row 0 column 9
...
row 0 column 25
row 0 column 29
...
row 31 column 25
row 31 column 29
3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
D0
2
Table
2
Digital video encoder
8. Transparent means
D1
row 0 column 0
row 0 column 4
row 0 column 8
...
row 0 column 24
row 0 column 28
...
row 31 column 24
row 31 column 28
1
1
pixel n
D0
10 of 84
0
0