SAA7103HV4 NXP Semiconductors, SAA7103HV4 Datasheet - Page 16

• Manufacturer Part Number: SAA7103HV4
• Manufacturer: NXP Semiconductors

Specifications of SAA7103HV4

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
SAA7102_SAA7103_4
Product data sheet
7.17 Programming the SAA7102; SAA7103
bytes following subaddress FFh. For further write access auto-incrementing of the LUT
address is performed. The cursor bit map access is similar to the LUT access but contains
only a single byte per address.
The I
In order to program the SAA7102; SAA7103 it is first necessary to determine the input
and output field timings. The timings are controlled by decoding binary counters that index
the position in the current line and field respectively. In both cases, 0 means the start of
the sync pulse.
At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the
index is 284, 702 pixels can be visible. Some variables are defined below:
The output lines should be centred on the screen. It should be noted that the encoder has
2 clocks per pixel; see
ADWHS = 256 + 710 − OutPix (60 Hz); ADWHS = 284 + 702 − OutPix (50 Hz);
ADWHE = ADWHS + OutPix × 2 (all frequencies)
For vertical, the procedure is the same. At 60 Hz, the first line with video information is
number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see
to
LAL = FAL + OutLin (all frequencies).
Most TV sets use overscan, and not all pixels respectively lines are visible. There is no
standard for the factor, it is highly recommended to make the number of output pixels and
lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output
pixels per line.
The total number of pixel clocks per line and the input horizontal offset need to be chosen
next. The only constraint is that the horizontal blanking has at least 10 clock pulses.
The required pixel clock frequency can be determined in the following way: Due to the
limited internal FIFO size, the input path has to provide all pixels in the same time frame
as the encoders vertical active time. The scaler also has to process the first and last
border lines for the anti-flicker function. Thus:
FAL
•
•
•
•
•
•
•
Table
InPix: the number of active pixels per input line
InPpl: the length of the entire input line in pixel clocks
InLin: the number of active lines per input field/frame
TPclk: the pixel clock period
OutPix: the number of active pixels per output line
OutLin: the number of active lines per output field
TXclk: the encoder clock period (37.037 ns)
2
=
C-bus slave address is defined as 88h.
19
72.
+
240 OutLin
---------------------------------
–
2
Rev. 04 — 18 January 2006
Table
(60 Hz);
62.
FAL
=
23
+
SAA7102; SAA7103
287 OutLin
---------------------------------
–
2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
(50 Hz);
Digital video encoder
Table 70
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