SAA7103HV4 NXP Semiconductors, SAA7103HV4 Datasheet - Page 14

• Manufacturer Part Number: SAA7103HV4
• Manufacturer: NXP Semiconductors

Specifications of SAA7103HV4

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
SAA7102_SAA7103_4
Product data sheet
7.12.5 Anti-taping (SAA7102 only)
7.13 RGB processor
7.14 Triple DAC
7.15 Timing generator
Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the
DACs corresponds to approximately 50 IRE.
It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times the
horizontal line frequency.
For more information contact your nearest Philips Semiconductors sales office.
This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be
fed to a SCART plug.
Before Y, C
difference signals and 2 times oversampling for luminance and 4 times oversampling for
color difference signals is performed. The transfer curves of luminance and color
difference components of RGB are illustrated in
Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the
output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal.
The CVBS output signal occurs with the same processing delay as the Y, C and optional
RGB or C
by
RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing
a 10-bit resolution.
The reference currents of all three DACs can be adjusted individually in order to adapt for
different output signals. In addition, all reference currents can be adjusted commonly to
compensate for small tolerances of the on-chip band gap reference voltage.
Alternatively, all currents can be switched off to reduce power dissipation.
All three outputs can be used to sense for an external load (usually 75 Ω) during a
pre-defined output. A flag in the I
not.
If the SAA7102; SAA7103 is required to drive a second (auxiliary) VGA monitor, the DACs
receive the signal directly from the cursor insertion block. In this event, the DACs are
clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video
encoder.
The synchronization of the SAA7102; SAA7103 is able to operate in two modes; Slave
mode and Master mode.
In Slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync),
VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can
be programmed. The frame sync signal is only necessary when the input signal is
15
⁄
16
with respect to Y and C DACs to make maximum use of the conversion ranges.
R
-Y-C
B
and C
B
outputs. Absolute amplitude at the input of the DAC for CVBS is reduced
R
signals are de-matrixed, individual gain adjustment for Y and color
Rev. 04 — 18 January 2006
2
C-bus status byte reflects whether a load is applied or
SAA7102; SAA7103
Figure 10
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
and
Figure
Digital video encoder
11.
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