SAA7103HV4 NXP Semiconductors, SAA7103HV4 Datasheet - Page 59

SAA7103HV4

Manufacturer Part Number
SAA7103HV4
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7103HV4

Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
PQFP
Pin Count
44
Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
SAA7102_SAA7103_4
Product data sheet
Table 81:
Table 82:
Bit
7
6
5
4
3
2
1 and 0 YPIX[9:8]
Bit
7
6
5
4
Symbol
EFS
PCBN
SLAVE
ILC
YFIL
HSL
Symbol
HFS
VFS
OFS
PFS
Scaler CTRL, MCB and YPIX register, subaddress 96h, bit description
Sync control register, subaddress 97h, bit description
Access Value Description
R/W
R/W
R/W
R/W
R/W
R/W
Access Value Description
R/W
R/W
R/W
R/W
Rev. 04 — 18 January 2006
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
in Slave mode frame sync signal at pin FSVGC
ignored
accepted
polarity of CBO signal
normal (HIGH during active video)
inverted (LOW during active video)
from the SAA7102; SAA7103 the timing to the graphics
controller is
master
slave
if hardware cursor insertion is active
set LOW for non-interlaced input signals
set HIGH for interlaced input signals
luminance sharpness booster
disabled
enabled
trigger event for the horizontal state machine (device is slave
to HSVGC input)
not shifted
shifted 128 PIXCLKs adapted to a late HSVGC
see
horizontal sync is derived from
input signal (Save mode) at pin HSVGC
a frame sync signal (Slave mode) at pin FSVGC (only if EFS
is set HIGH)
vertical sync (field sync) is derived from
input signal (Slave mode) at pin VSVGC
a frame sync signal (Slave mode) at pin FSVGC (only if EFS
is set HIGH)
pin FSVGC is
input
active output
polarity of signal at pin FSVGC in output mode (Master
mode) is
active HIGH; rising edge of the input signal is used in Slave
mode
active LOW; falling edge of the input signal is used in Slave
mode
Table 80
SAA7102; SAA7103
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Digital video encoder
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