SAA7103HV4 NXP Semiconductors, SAA7103HV4 Datasheet - Page 57

SAA7103HV4

Manufacturer Part Number
SAA7103HV4
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7103HV4

Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
PQFP
Pin Count
44
Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
SAA7102_SAA7103_4
Product data sheet
Table 70:
Table 71:
Table 72:
Legend: * = default value after reset.
Table 73:
[1]
Table 74:
Bit
7 to 0 FAL[7:0]
Bit
7 to 0 LAL[7:0]
Bit
7
6
5
4
3
2
1
0
Subaddress Bit
7Eh
7Fh
Subaddress Bit
81h
82h
83h
This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.
Symbol
Symbol
Symbol
TTX60
LAL8
-
FAL8
TTXEVE8
TTXOVE8
TTXEVS8
TTXOVS8
First active line register, subaddress 7Ah, bit description
Last active line register, subaddress 7Bh, bit description
TTX mode, MSB vertical register, subaddress 7Ch, bit description
Disable TTX line registers, subaddresses 7Eh and 7Fh, bit description
Pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description
7 to 0 LINE[12:5]
7 to 0 LINE[20:13] R/W
7 to 0 PCL[07:00] R/W
7 to 0 PCL[15:08]
7 to 0 PCL[23:16]
Symbol
Symbol
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 04 — 18 January 2006
00h
00h
0*
1
0
Access Value
Access Value Description
R/W
with FAL8 (see
M-systems and (FAL + 1) for other systems, measured in
lines
coincides with the first field synchronization pulse
with LAL8 (see
M-systems and LAL for other system, measured in lines
coincides with the first field synchronization pulse
enables NABTS (FISE = 1) or European TTX (FISE = 0)
enables world standard teletext 60 Hz (FISE = 1)
see
must be programmed with logic 0 to ensure compatibility to
future enhancements
see
see
see
see
see
Table 71
Table 70
Table 69
Table 67
Table 68
Table 66
20 F63Bh 640 × 480 to NTSC M
1B 5A73h 640 × 480 to PAL B/G (as by strapping
-
-
SAA7102; SAA7103
individual lines in both fields (PAL counting)
can be disabled for insertion of teletext by the
respective bits, disabled line = LINExx (50 Hz
field rate)
Table
Table
Description
defines the frequency of the synthesized
pixel clock PIXCLKO;
f
pins)
f
XTAL
PIXCLK
72) first active line = (FAL + 4) for
72) last active line = (LAL + 3) for
= 27 MHz nominal
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
=
PCL
---------- -
2
24
Digital video encoder
×
f
XTAL
×
[1]
8
;
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