L-USS820D-DB LSI, L-USS820D-DB Datasheet - Page 14

• Manufacturer Part Number: L-USS820D-DB
• Manufacturer: LSI

Specifications of L-USS820D-DB

• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

USS-820D
USB Device Controller
Register Interface
In this case, the SBI/SBI1 bit will be set even though
there is no corresponding data set present in the
receive FIFO. Therefore, firmware must be prepared to
service a receive done interrupt where no data sets are
present in the indicated FIFO.
Table 9 shows the values loaded into each of the stan-
dard copies of the shared register bits when firmware
resets the PEND register bit
Table 9. Shared Register Update Values When
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14
Register
RXSTAT RXSETUP Loaded with pended copy if
RXSTAT
EPCON
SOFH
SOFH
SOFL
SBI1
SSR
SBI
Firmware Resets PEND
EDOVW Set to 1 if standard copy = 1 or
RESET
RXSTL
All bits
All bits
All bits
ASOF
Bit(s)
TS
Set to 1 if standard copy = 1 or
pended copy = 1.
Set to 1 if standard copy = 1 or
pended copy = 1.
USB action updated RXSETUP
while PEND was set.
pended copy = 1.
Set to 1 if standard copy = 1 or
pended copy = 1.
Set to 1 if standard copy = 1 or
pended copy = 1.
Loaded with pended copy if
USB SOF was received while
PEND was set.
Loaded with pended copy if
USB SOF was received while
PEND was set.
Set to 1 if standard copy = 1 or
pended copy = 1.
(continued)
.
Update Value
The register bits that are only updated by firmware, but
reside in registers with shared bits and must therefore
be updated only while PEND is set, are shown in
Table 10.
Table 10. Register Bits Only Updated While PEND
Firmware should attempt to minimize the period during
which PEND is set in order to minimize the distortion of
the detection of hardware events.
Register Reads with Side Effects
In general, USS-820D register reads do not have side
effects—they do not cause any device state to change.
The following are exceptions to this rule:
Register
RXSTAT
RXDAT reads cause the internal RX FIFO read
pointer to change and possibly cause the
RXFLG.RXURF register bit to SET.
RXCNTH/RXCNTL reads while RXFLG.RXFIF = 00
cause the RXFLG.RXURF register bit to SET.
LOCK reads restart the register unlock sequence
after SUSPEND (described in Special Action
Required by USS-820/USS-825 After Suspend—
AP97-058CMPR-04).
Any register reads during a register unlock sequence
after SUSPEND, other than the LOCK register,
cause the unlock sequence to fail and require the
sequence to be restarted.
EPCON
SOFH
SSR
is Set
RXSEQ
All bits except RXSTL
SOFIE, SOFODIS
SUSPPO, SUSPDIS, RESUME,
SUSPEND
Bit(s)
Data Sheet, Rev. 7
September 2004
Agere Systems Inc.