L-USS820D-DB LSI, L-USS820D-DB Datasheet - Page 26

• Manufacturer Part Number: L-USS820D-DB
• Manufacturer: LSI

Specifications of L-USS820D-DB

• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

USS-820D
USB Device Controller
USB Device Controller
Register Interface
Table 24. USB Transmit FIFO Control Register (TXCON)—Address: 03H; Default: 0000 0100B
This register controls the transmit FIFO specified by EPINDEX. This register is endpoint indexed.
* Assumes MCSR.FEAT = 1. If MCSR.FEAT = 0, these FFSZ settings indicate 64 bytes.
† ATM mode is recommended for normal operation. ADVRM and REVRP, which control the read marker and read pointer when ATM = 0, are
26
used for test purposes.
Bit
6:5
TXCLR
7
4
3
2
1
0
Bit 7
FFSZ[1:0] FIFO Size. These bits select the size of the transmit FIFO.
Symbol
ADVRM
REVRP
TXCLR
TXISO
ATM
—
FFSZ1
R/W
Bit 6
Transmit FIFO Clear. Setting this bit flushes the transmit FIFO, resets all the read/write
pointers and markers, resets the TXCNTH and TXCNTL registers, resets the TXFLUSH,
TXVOID, TXERR, and TXACK bits of the TXSTAT register, sets the TXEMP bit in TXFLG,
and clears all other bits in TXFLG. Hardware clears this bit after the flush. Setting this bit
does not affect the TXSEQ bit in the TXSTAT register. This bit should only be set when the
endpoint is known to be inactive or there is a FIFO error present.
Reserved. Write 0 to this bit. Reads always return 0.
Transmit Isochronous Data. Firmware sets this bit to indicate that the transmit FIFO
contains isochronous data. The SIE uses this bit to determine if a handshake is required at
the end of a transmission.
Automatic Transmit Management.
pointer and read marker to be adjusted automatically as indicated:
1. To origin of next data set.
2. To origin of the data set last read.
This bit should always be set, except for test purposes. Setting this bit disables ADVRM
and REVRP. This bit can be set and cleared by firmware. Hardware neither clears nor sets
this bit. This bit must always be set for isochronous endpoints (TXISO = 1).
Advance Read Marker Control (Non-ATM Mode Only).
next packet transmission by advancing the read marker to the origin of the next data
packet (the position of the read pointer). Hardware clears this bit after the read marker is
advanced. This bit is effective only when the REVRP, ATM, and TXCLR bits are clear.
Reverse Read Pointer (Non-ATM Mode Only).
same data stack may need to be available for retransmit. Setting this bit reverses the read
pointer to point to the origin of the last data set (the position of the read marker) so that the
SIE can reread the last set for retransmission. Hardware clears this bit after the read
pointer is reversed. This bit is effective only when the ADVRM, ATM, and TXCLR bits are
all clear.
FFSZ[1:0]
(continued)
Status
NACK
ACK
00
01
10
11
FFSZ0
Bit 5
Read Pointer
Reversed (2)
Unchanged
Nonisochronous Size
Bit 4
—
—
32*
16
64
8*
Read Marker
Advanced (1)
Unchanged
Function/Description
†
TXISO
Setting this bit (the default value) causes the read
Bit 3
Isochronous Size
†
1024
256
512
In the case of a bad transmission, the
64
Bit 2
ATM
†
Setting this bit prepares for the
R/W
ADVRM
Bit 1
Data Sheet, Rev. 7
September 2004
Agere Systems Inc.
REVRP
Bit 0