L-USS820D-DB LSI, L-USS820D-DB Datasheet - Page 18

• Manufacturer Part Number: L-USS820D-DB
• Manufacturer: LSI

Specifications of L-USS820D-DB

• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

USS-820D
USB Device Controller
USB Device Controller
Register Interface
Table 15. Start of Frame High Register (SOFH)—Address: 0FH; Default: 0000 0000B
This register contains isochronous data transfer enable and interrupt bits and the upper 3 bits of the 11-bit time
stamp received from the host.
* S = shared bit. P = PEND must be set when writing this bit. See Special Firmware Action for Shared Register Bits section.
18
SOFACK
Bit 7
Bit
2:0
R
7
6
5
4
3
SOFODIS SOF Pin Output Disable. When set, no low pulse is driven to the SOF pin in
SOFACK
FTLOCK
TS[10:8]
Symbol
R/W (S*)
SOFIE
ASOF
ASOF
Bit 6
(continued)
SOF Token Received Without Error (Read Only). When set, this bit signifies that
the 11-bit time stamp stored in SOFL and SOFH is valid. This bit is updated every
time an SOF token is received from the USB bus, and it is cleared when an artificial
SOF is generated by the frame timer. This bit is set and cleared by hardware.
Any Start of Frame. This bit is set by hardware to signify that a new frame has
begun. The interrupt can result either from the reception of an actual SOF packet or
from an artificially generated SOF from the frame timer. This interrupt is asserted in
hardware even if the frame timer is not locked to the USB bus frame timing. When
set, this bit indicates that either the actual SOF packet was received or an artificial
SOF was generated by the frame timer.
Setting this bit to 1 by firmware has the same effect as when it is set by hardware.
This bit must be cleared to 0 by firmware if SOFODIS = 1 or if MCSR.FEAT = 1. If
SOFODIS and MCSR.FEAT = 0, this bit clears itself after one t
system to detect start of frame via the SOFN device pin.
This bit also serves as the SOF interrupt flag. This interrupt is only asserted in hard-
ware if the SOF interrupt is enabled (SOFIE set) and the interrupt channel is enabled.
SOF Interrupt Enable. When set, setting the ASOF bit causes an interrupt request to
be generated if the interrupt channel is enabled. Hardware reads this bit but does not
write to it.
Frame Timer Lock (Read Only). When set, this bit signifies that the frame timer is
presently locked to the USB bus frame time. When cleared, this bit indicates that the
frame timer is attempting to synchronize the frame time.
response to setting the ASOF bit. The SOF pin is driven to 1 when SOFODIS is set.
When this bit is clear, setting the ASOF bit causes the SOF pin to be toggled with a
low pulse for eight t
Time Stamp Received from Host. TS[10:8] are the upper 3 bits of the 11-bit frame
number issued with an SOF token. This time stamp is valid only if the SOFACK bit is
set.
R/W (P*)
SOFIE
Bit 5
FTLOCK
Bit 4
CLK
R
periods.
SOFODIS
Function/Description
R/W (P*)
Bit 3
TS10
Bit 2
R/W (S*)
CLK
Bit 1
Data Sheet, Rev. 7
TS9
September 2004
, which requires the
Agere Systems Inc.
Bit 0
TS8