L-USS820D-DB LSI, L-USS820D-DB Datasheet - Page 39

• Manufacturer Part Number: L-USS820D-DB
• Manufacturer: LSI

Specifications of L-USS820D-DB

• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Data Sheet, Rev. 7
September 2004
Agere Systems Inc.
Register Interface
Table 37. Data Set Available (DSAV)—Address: 1DH; Default: 0000 0000B
This register contains receive/transmit data set available bits.
Table 38. Data Set Available (DSAV1)—Address: 1EH; Default: 0000 0000B
This register contains receive/transmit data set available bits.
Bit
Bit
RXAV3
RXAV7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit 7
Bit 7
R
R
Symbol
Symbol
RXAV3
RXAV2
RXAV1
RXAV0
RXAV7
RXAV6
RXAV5
RXAV4
TXAV3
TXAV2
TXAV1
TXAV0
TXAV7
TXAV6
TXAV5
TXAV4
TXAV3
TXAV7
Bit 6
Bit 6
R
R
Receive/Transmit Data Set Available. This feature is only available if MCSR.FEAT = 1
or TXDSAM = 1; otherwise, reads 0. May be used to improve firmware efficiency when
polling endpoints. For receive FIFOs, this register indicates that one or more data sets
are available to be read. For transmit FIFOs, this register indicates that one or more data
sets are available to be written. Bits always read 0 for endpoints which are not enabled
(RXEPEN/TXEPEN = 0). If a transmit endpoint has TXDSAM = 1, the corresponding
RXAV/TXAV bit of the DSAV register indicates instead that the TXVOID bit is set (a NAK
has been sent to the host). This usage when TXDSAM = 1 does not require
MCSR.FEAT = 1.
Receive/Transmit Data Set Available. This feature is only available if MCSR.FEAT = 1
or TXDSAM = 1; otherwise, reads 0. May be used to improve firmware efficiency when
polling endpoints. For receive FIFOs, this register indicates that one or more data sets
are available to be read. For transmit FIFOs, this register indicates that one or more data
sets are available to be written. Bits always read 0 for endpoints which are not enabled
(RXEPEN/TXEPEN = 0). If a transmit endpoint has TXDSAM = 1, the corresponding
RXAV/TXAV bit of the DSAV register indicates instead that the TXVOID bit is set (a NAK
has been sent to the host). This usage when TXDSAM = 1 does not require
MCSR.FEAT = 1.
(continued)
RXAV2
RXAV6
Bit 5
Bit 5
R
R
TXAV2
TXAV6
Bit 4
Bit 4
R
R
Function/Description
Function/Description
RXAV1
RXAV5
Bit 3
Bit 3
R
R
TXAV1
TXAV5
Bit 2
Bit 2
R
R
USB Device Controller
RXAV0
RXAV4
Bit 1
Bit 1
R
R
USS-820D
TXAV0
TXAV4
Bit 0
Bit 0
R
R
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