L-USS820D-DB LSI, L-USS820D-DB Datasheet - Page 42

• Manufacturer Part Number: L-USS820D-DB
• Manufacturer: LSI

Specifications of L-USS820D-DB

• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

USS-820D
USB Device Controller
USB Device Controller
Firmware Responsibilities for USB
SETUP Commands
Firmware must keep track of the direction of data flow
during a control transfer, and detect the start of the
status stage by a change in that direction. For control
OUT transfers, the status stage will be an IN, and the
firmware should write a zero-byte data packet to the
transmit FIFO, assuming the command completed
successfully. For control IN transfers, the status stage
will be an OUT, and the firmware should read the data
packet and set the RXFFRC register bit (like any other
OUT transfer), again assuming the command
completed successfully. This will cause an ACK to be
sent to the host, indicating a successful completion.
Firmware should stall endpoint 0 if it receives a stan-
dard command that does not match any of the defined
commands or a valid command that contains a param-
eter with a bad value (e.g., GET_STATUS[Endpoint x]
when endpoint x is not enabled). Firmware should also
stall if the data stage of a control transaction attempts
to transfer more bytes than were indicated by the
SETUP stage.
Firmware must interpret any vendor or class
commands as defined by the application.
Other Firmware Responsibilities
Table 40. Other Firmware Responsibilities
42
USB Event
SUSPEND
RESUME
RESET
USB
USB
and
USB RESET can be detected by
reading a 1 from the RESET bit of the
SSR register. If the USB interrupt is
enabled (IE_RESET), this will be indi-
cated by the IRQN output. At that time,
firmware must reset any information it
maintains regarding endpoints, inter-
faces, alternate settings, and configura-
tions. All RXEPEN and TXEPEN
endpoints should be set to 0, except for
endpoint 0, which should be set to 1.
The function address register FADDR
should be set to 0. The data toggle bits
for all endpoints should be set to 0 as
well. If MCSR.FEAT = 1, FADDR is
automatically cleared to 0 when USB
RESET is detected.
Firmware must manage the SUSPEND
and RESUME register bits, as docu-
mented in the following section, in order
to meet the USB specifications for bus-
powered devices.
Firmware Responsibility
(continued)
Frame Timer Behavior
The USS-820D contains an internal frame timer that
allows the device to lock to the USB host frame timer,
and to synthesize lost SOF packets, as required by the
USB specification. The frame timer requires three valid
SOF packets from the host in order to lock to the host
frame timer. This locked status is indicated by the
FTLOCK status bit in SOFH. In order to achieve this
lock, the interval between each SOF must be within
45 clocks of the nominal 12,000 clocks, and the
successive intervals must be within two clocks of each
other. Both of these conditions will be true in a correctly
functioning system with no bus errors. While the frame
timer is locked, it will synthesize SOFs by setting
ASOF, generating an SOF interrupt (if SOFIE = 1), and
asserting the SOFN pin (if SOFODIS = 0) for up to
three consecutive frames if SOF packets are no longer
received from the host. The frame timer will become
unlocked under any of the following conditions:
SUSPEND and RESUME Behavior
In the following sections describing SUSPEND and
RESUME behavior, the following terminology is used:
Hard or soft RESET.
USB RESET.
The device goes suspended.
No SOF packets are received from the host for three
frames.
An SOF is received that violates the USB specifica-
tion for frame interval or previous frame length com-
parison.
Device—The entire product that contains the USS-
820D, such as a modem or printer.
Application—All electronic components of the device
other than the USS-820D, such as a microcontroller,
RAM, power control logic, RESET logic, or crystal.
Firmware—Code running on the microcontroller
which is part of the application.
Controller—That intelligent part of the application
which uses the USS-820D address, data and read/
write pins to access its internal registers.
Powered-off components—Those parts of the appli-
cation which are connected to the USS-820D and
powered off during SUSPEND, for example, a micro-
controller or RAM.
Hardware—Logic inside the USS-820D.
Data Sheet, Rev. 7
September 2004
Agere Systems Inc.