L-USS820D-DB LSI, L-USS820D-DB Datasheet - Page 36

• Manufacturer Part Number: L-USS820D-DB
• Manufacturer: LSI

Specifications of L-USS820D-DB

• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

USS-820D
USB Device Controller
USB Device Controller
Register Interface
Table 31. System Status Register (SSR)—Address: 12H; Default: 0000 0000B
This register allows control and monitoring of the USB SUSPEND and RESET events.
* S = shared bit. P = PEND must be set when writing this bit. See Special Firmware Action for Shared Register Bits section.
Table 32. Hardware Revision Register (REV)—Address: 18H; Default: 0001 0011B
This register contains the hardware revision number, which will be incremented for each version of the hardware.
This will allow firmware to query the hardware status and determine which functions or features are supported.
36
7:5
Bit
4
3
2
1
0
Bit
7:4
3:0
Bit 7
Bit 7
SUSPEND SUSPEND Detected (Read Only)/SUSPEND Control (Write Only). For a complete descrip-
SUSPDIS
RESUME
SUSPPO
Symbol
RESET
—
Main Hardware Revision Number
Symbol
—
—
Reserved. Write 0s to these bits. Reads always return 0s.
SUSPEND Power Off. This bit must be set by firmware if externally connected devices will be
powered off during a SUSPEND. The correct value of this bit must be established before firm-
ware suspends the USS-820D and should only need to be done once at device initialization
time.
SUSPEND Disable. When asserted, this bit disables the detection of a USB SUSPEND event.
This bit is for test purposes and should not be set during normal system operation.
RESUME Detected. For a complete description of the use of this bit, see the SUSPEND and
RESUME Behavior section of this document. When set, the USS-820D has detected and
responded to a wake-up condition, either global or remote. A global RESUME is indicated
when the host asserts a non-IDLE state on the USB bus. A remote wake-up is indicated when
the device asserts the RWUPN input pin (if that feature is enabled by the RWUPE bit). This bit
should be reset by firmware as soon as possible after resuming to allow the next SUSPEND
event to be detected.
tion of the use of this bit, see the SUSPEND and RESUME Behavior section of this document.
This bit serves as both a read-only status bit and a write-only control bit. For this reason, firm-
ware cannot do a simple read/modify/write sequence to update this register. Firmware must
always explicitly specify the correct value of this SUSPEND control bit when writing SSR. The
read-only status bit is set by hardware when a SUSPEND condition is detected on the USB
bus, and clears itself after the SUSPEND condition ceases and the device resumes. The bit
will remain set during device wake-up. The value of this read-only bit is not affected by firm-
ware writes. The write-only control bit is only updated by firmware, and is used to suspend the
device by setting the bit to 1, and then setting the bit to 0. This write sequence will cause the
device to SUSPEND regardless of the initial value of the bit, which cannot be read.
USB RESET Detected. When set, a RESET condition is detected on the USB bus. If interrupt
is enabled (T_IRQ and IE_RESET set), an interrupt is generated to the controller. Firmware
clears this bit.
Bit 6
Bit 6
—
—
Main Hardware Revision Number.
Subhardware Revision Number.
(continued)
Bit 5
Bit 5
SUSPPO
Bit 4
Bit 4
Function/Description
R
SUSPDIS
Function/Description
R/W (P*)
Bit 3
Bit 3
Subhardware Revision Number
RESUME
Bit 2
Bit 2
SUSPEND
R
Bit 1
Bit 1
Data Sheet, Rev. 7
W (P*)
September 2004
Agere Systems Inc.
R/W (S*)
RESET
Bit 0
Bit 0