L-USS820D-DB LSI, L-USS820D-DB Datasheet - Page 33

• Manufacturer Part Number: L-USS820D-DB
• Manufacturer: LSI

Specifications of L-USS820D-DB

• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Data Sheet, Rev. 7
September 2004
Agere Systems Inc.
Register Interface
Table 29. Receive FIFO Flag Register (RXFLG)—Address: 09H; Default: 0000 1000B (continued)
Bit
7:6
5
4
3
2
1
RXFIF[1:0]
RXFLUSH
RXFULL
Symbol
RXEMP
RXURF
—
Receive FIFO Index Flags (Read Only) (continued).
For traceability, the RXFIF flags must be checked before and after reads from the receive
FIFO and the setting of RXFFRC in RXCON.
Note: To simplify firmware development, it is recommended that control endpoints are
Reserved. Write 0s to these bits. Reads always return 0s.
Receive FIFO Flush (Read Only). Only available if MCSR.FEAT = 1. Updated at every
SOF, and only used for isochronous endpoints. RXFIF bits are set when valid data sets
are received from the host. For isochronous endpoints, this RXFIF increment does not
occur until the next SOF. During that subsequent frame, it is the responsibility of firmware
to read out the data set. If that read is not completed (RXFFRC set by firmware) by the
time the next SOF is received, that data set is flushed from the receive FIFO—RXFIF is
decremented by hardware. This flush is indicated by hardware by setting the RXFLUSH
bit. While this bit is set, the affect of firmware receive FIFO data (RXDAT) reads is
blocked, in order to stop potential corruption of a new data set. Before firmware sets
RXFFRC (for isochronous endpoints only), it must first check RXFLUSH. If RXFLUSH is
set, firmware must discard the data set which it just read, because it is potentially
corrupted. This situation should only occur if firmware is late in reading out a data set
(read not completed before SOF). Firmware must not be late on consecutive frames—
this will cause a loss of frame/data synchronization with the host—data sets may be
visible to firmware during the wrong frame. Firmware must always set RXFFRC at the
end of a data set read, even if RXFLUSH = 1. RXFLUSH is reset to 0 by the setting of
RXFFRC to 1.
Receive FIFO Empty Flag (Read Only). Hardware sets this flag when there are no data
bytes present in the data set currently being read. Hardware clears the bit when the
empty condition no longer exists. This bit always tracks the current status of the receive
FIFO, regardless of isochronous or nonisochronous mode.
Receive FIFO Full Flag (Read Only). Hardware sets this flag when the data set
currently being read contains the same number of data bytes as the size of the FIFO.
Hardware clears the bit when the full condition no longer exists. This bit always tracks
the current status of the receive FIFO regardless of isochronous or nonisochronous
mode.
Receive FIFO Underrun Flag (Read, Clear Only). Hardware sets this bit when an addi-
tional byte is read from an empty receive FIFO or when RXCNTH or RXCNTL is read
while RXFIF[1:0] = 00. Hardware does not clear this bit, so it must be cleared by firm-
ware through RXCLR. When the receive FIFO underruns, the read pointer does not
advance. It remains locked in the empty position.
When this bit is set, all transmissions are NACKed.
In isochronous mode, RXOVF, RXURF, and RXFIF are handled using the following rule:
firmware events cause status change immediately, while USB events cause status
change only at SOF. Since underrun can only be caused by firmware, RXURF is updated
immediately. The RXURF flag must be checked after reads from the receive FIFO before
setting the RXFFRC bit in RXCON.
Note: When this bit is set, the FIFO is in an unknown state. It is recommended that the
(continued)
used in single-packet mode only.
FIFO is reset in the error management routine using the RXCLR bit in the RXCON
register.
Function/Description
USB Device Controller
USS-820D
33