XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 158

• Manufacturer Part Number: XC3S500E-4FT256I
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DC and Switching Characteristics
Byte Peripheral Interface (BPI) Configuration Timing
Table 120: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
158
T
T
T
T
T
T
T
T
(Open-Drain)
Symbol
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
PROG_B
LDC[2:0]
HSWAP
CSO_B
A[23:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
D[7:0]
CCLK
HDC
Figure 78: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration (BPI-DN mode shown)
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising
edge of INIT_B
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising
edge of INIT_B
Minimum period of initial A[23:0] address cycle;
LDC[2:0] and HDC are asserted and valid
Address A[23:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
T
MINIT
<0:1:0>
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High.
Description
000_0000
T
CCLK1
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Byte 0
T
INITADDR
000_0001
(M[2:0]=<0:1:0>)
(M[2:0]=<0:1:1>)
BPI-DN:
BPI-UP:
Byte 1
T
AVQV
Data
Minimum
New ConfigRate active
T
50
Address
CCLK1
0
5
2
T
DS312-3 (v3.8) August 26, 2009
CCO
Data
T
See
See
See
See
See
DCC
T
Maximum
Product Specification
CCLKn
Table 112
Table 112
Table 116
Table 116
Table 116
Address
Data
5
2
-
-
DS312-3_08_032409
Address
T
CCD
T
cycles
Units
Data
CCLK1
ns
ns
R