XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 166

• Manufacturer Part Number: XC3S500E-4FT256I
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pinout Descriptions
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx® web site at the specified location
in
Table 127: Xilinx Package Mechanical Drawings and Material Declaration Data Sheets
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in
Table 128: Power and Ground Supply Pins by Package
166
VQ100
VQG100
CP132
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
Package
Table
127.
Package
VCCINT
16
16
4
6
4
4
8
8
VCCAUX
10
4
4
4
8
8
8
8
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
VCCO
12
16
20
24
28
8
8
9
Table
Package Drawing
128.
GND
12
16
13
20
28
28
42
48
www.xilinx.com
Material Declaration Data Sheets (MDDS) are also avail-
able on the
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in
imum number of single-ended I/O pins available, assuming
that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are
used as general-purpose I/O. Likewise, the table shows the
maximum number of differential pin-pairs available on the
package. Finally, the table shows how the total maximum
user-I/Os are distributed by pin type, including the number
of unconnected—i.e., N.C.—pins on the device.
Xilinx web site
PK173_VQ100
PK130_VQG100
PK147_CP132
PK101_CPG132
PK169_TQ144
PK126_TQG144
PK166_PQ208
PK123_PQG208
PK158_FT256
PK115_FTG256
PK152_FG320
PK106_FGG320
PK182_FG400
PK108_FGG400
PK183_FG484
PK110_FGG484
Table
for each package.
129. The table shows the max-
DS312-4 (v3.8) August 26, 2009
MDDS
Product Specification
R