XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 21

• Manufacturer Part Number: XC3S500E-4FT256I
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Configurable Logic Block (CLB) and
Slice Resources
For additional information, refer to the “Using Configurable
Logic Blocks (CLBs)” chapter in UG331.
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to imple-
ment logic and two dedicated storage elements that can be
used as flip-flops or latches. The LUTs can be used as a
Table 9: Spartan-3E CLB Resources
Slices
Each CLB comprises four interconnected slices, as shown
in
organized as a column with an independent carry chain.
The left pair supports both logic and memory functions and
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the
DS312-2 (v3.8) August 26, 2009
Product Specification
Notes:
1.
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Figure
Device
The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see
16. These slices are grouped in pairs. Each pair is
R
Rows
CLB
22
34
46
60
76
Columns
Figure 1
CLB
16
26
34
46
58
Spartan-3E
FPGA
in Module 1).
Total
1,164
2,168
3,688
CLB
240
612
(1)
Figure 14: CLB Locations
14,752
Slices
4,656
2,448
8,672
960
www.xilinx.com
CLB
Flip-Flops
X0Y3
X0Y2
X0Y1
X0Y0
16x1 memory (RAM16) or as a 16-bit shift register (SRL16),
and additional multiplexers and carry logic simplify wide
logic and arithmetic functions. Most general-purpose logic
in a design is automatically mapped to the slice resources in
the CLBs. Each CLB is identical, and the Spartan-3E family
CLB structure is identical to that for the Spartan-3 family.
CLB Array
The CLBs are arranged in a regular array of rows and col-
umns as shown in
Each density varies by the number of rows and columns of
CLBs (see
LUTs support both logic and memory (including both
RAM16 and SRL16 shift registers) while half support logic
only, and the two types alternate throughout the array col-
umns. The SLICEL reduces the size of the CLB and lowers
the cost of the device, and can also provide a performance
advantage over the SLICEM.
LUTs /
17,344
29,504
1,920
4,896
9,312
Slice
X1Y3
X1Y2
X1Y1
X1Y0
Table
IOBs
Logic Cells
X2Y3
X2Y2
X2Y1
X2Y0
Equivalent
10,476
19,512
33,192
9).
2,160
5,508
Figure
X3Y3
X3Y2
X3Y1
X3Y0
DS312-2_31_021205
14.
RAM16 /
SRL16
14,752
2,448
4,656
8,672
960
Functional Description
Distributed
RAM Bits
138,752
236,032
15,360
39,168
74,496
21