XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 66

• Manufacturer Part Number: XC3S500E-4FT256I
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
The four types of general-purpose interconnect available in
each channel, shown in
Long Lines
Each set of 24 long line signals spans the die both horizon-
tally and vertically and connects to one out of every six inter-
connect tiles. At any tile, four of the long lines drive or
receive signals from a switch matrix. Because of their low
capacitance, these lines are well-suited for carrying
high-frequency signals with minimal loading effects (e.g.
skew). If all global clock lines are already committed and
additional clock signals remain to be assigned, long lines
serve as a good alternative.
Hex Lines
Each set of eight hex lines are connected to one out of
every three tiles, both horizontally and vertically. Thirty-two
hex lines are available between any given interconnect tile.
Hex lines are only driven from one end of the route.
Double Lines
Each set of eight double lines are connected to every other
tile, both horizontally and vertically. in all four directions.
Thirty-two double lines available between any given inter-
connect tile. Double lines are more connections and more
flexibility, compared to long line and hex lines.
Direct Connections
Direct connect lines route signals to neighboring tiles: verti-
cally, horizontally, and diagonally. These lines most often
drive a signal from a "source" tile to a double, hex, or long
line and conversely from the longer interconnect back to a
direct line accessing a "destination" tile.
66
Direct Connections
Figure 50: Interconnect Types between Two Adjacent Interconnect Tiles (Continued)
Figure
50, are described below.
www.xilinx.com
CLB
CLB
CLB
Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E
FPGAs have two global logic control signals, as described
in
cation via the STARTUP_SPARTAN3E primitive.
Table 43: Spartan-3E Global Logic Control Signals
The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
GSR control instead of a separate global reset signal in the
design to free up CLB inputs, resulting in a smaller, more
efficient design. Similarly, the GSR signal is asserted auto-
matically during the FPGA configuration process, guaran-
teeing that the FPGA starts-up in a known state.
The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
MBT signals are for
figuration Images Using MultiBoot Option, page
CLK input is an alternate clock for configuration
page
Control Input
Table
Global
107.
GSR
GTS
CLB
CLB
CLB
43. These signals are available to the FPGA appli-
DS312-2_12_020905
Global Set/Reset: When High,
asynchronously places all registers and
flip-flops in their initial state (see
Initialization, page
automatically during the FPGA
configuration process (see
page
Global Three-State: When High,
asynchronously forces all I/O pins to a
high-impedance state (Hi-Z,
three-state).
CLB
CLB
CLB
Dynamically Loading Multiple Con-
107).
DS312-2 (v3.8) August 26, 2009
Description
32). Asserted
Product Specification
Start-Up,
Start-Up,
93. The
R