NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet
NQE7520MC S L7RD
Specifications of NQE7520MC S L7RD
Related parts for NQE7520MC S L7RD
NQE7520MC S L7RD Summary of contents
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... E7520 Memory Controller Hub (MCH) Specification Update July 2009 Notice: The Intel® E7520 MCH may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update. Document Number: 303041-004 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. Intel, Intel Xeon, Intel NetBurst, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...
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... Contents Revision History ................................................................................................................. 4 Preface ............................................................................................................................... 5 Summary Table of Changes ............................................................................................... 6 Identification Information .................................................................................................... 9 Errata................................................................................................................................ 10 Specification Changes...................................................................................................... 21 Specification Clarifications................................................................................................ 22 Documentation Changes.................................................................................................. 23 ® Intel E7520 Memory Controller Hub (MCH) Specification Update 3 ...
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... Initial publication. -002 • Added C4 Stepping information. • Added errata 30-32. -003 • Added Specification Clarification 1. -004 • Added Errata 35 4 Description ® Intel E7520 Memory Controller Hub (MCH) Specification Update Date June 2004 November 2004 June 2005 July 2009 ...
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... E7520 Memory Controller Hub (MCH) Datasheet Nomenclature Errata are design defects or errors. These may cause the Intel published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. ...
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... Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the E7520 MCH. Intel may fix some errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: ...
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... System marginalities may result in spurious link-down error events on power state changes Fix Possible loss of Hot-swap Power Fault Event in dual PCI Express Hot-swap port configurations Fixed Memory initialization may fail at low temperatures ® Intel E7520 Memory Controller Hub (MCH) Specification Update Summary Table of Changes ERRATA 7 ...
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... Specification Changes Number None for this revision of the Specification Update Specification Clarifications Number 1 Clarification to Section 4.4.1, “Memory Remapping”, in the EDS Documentation Changes Number 1 Interupt Redirection 8 SPECIFICATION CHANGES SPECIFICATION CLARIFICATIONS DOCUMENTATION CHANGES ® Intel E7520 Memory Controller Hub (MCH) Specification Update ...
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... Identification Information Component Identification via Programming Interface ® The Intel E7520 MCH can be identified by the following register contents: MCH Version E7520 E7520 E7520 NOTES: 1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00 - 01h in the PCI bus 0, device 0, function 0 configuration space. ...
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... Implication: Correctable and uncorrectable memory errors may be detected since ECC is not properly initialized. The entire memory array is not initialized with zeros. Refer to your Intel representative for details Workaround: For the steppings effected, see the Summary Table of Changes. Status: 4 ...
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... Alternatively in MSI mode, software may poll for command complete rather than wait for MSI, or implement the command complete timeout to continue to the next slot control update rather than repeat the current slot control update. Status: For the steppings effected, see the Summary Table of Changes. ® Intel E7520 Memory Controller Hub (MCH) Specification Update Errata 11 ...
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... Implication: A spurious error is flagged, and accesses between 4 GB and 32 GB will not succeed in the 32 GB (maximum) memory configuration, which can result in a system hang. Refer to your Intel representative for details the Intel Workaround: Controller Hub (MCH) Components BIOS Specification for details. ...
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... Implication: across both the primary and mirror DIMMs. Workaround: Refer to the E7520, E7320 and E7525 BIOS Specification Update for workaround details. Status: For the steppings effected, see the Summary Table of Changes. ® Intel E7520 Memory Controller Hub (MCH) Specification Update Errata 13 ...
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... DRAM_SEC2_ADD It is not possible to determine which of two DIMMs incurred an SEC or DED error with memory Implication: mirroring enabled. Workaround: Refer to your Intel Representative for workaround details. Status: For the steppings effected, see the Summary Table of Changes. 18. MCH transitions from Polling.Active prematurely During a standard link training sequence, the MCH should remain in Polling.Active until TS1 Problem: ordered sets with link and lane set to PAD are received on all lanes that passed Receiver Detect ...
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... Demand scrubbing can be enabled and disabled by updating the Scrub Limit and Control Register (SCRUBLIM Device 8, Function 0, Offset C8-CBh bit 27). For the steppings effected, see the Summary Table of Changes. Status: ® Intel E7520 Memory Controller Hub (MCH) Specification Update Errata 15 ...
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... Requests after reset. In order to ensure the ability of the system to successfully enumerate PCI devices, BIOS should disable PCI Express Completion Timeout in the root port configuration of MCH links connected to Intel® 6700PXH 64-bit PCI Hub, Intel® IOP332, and Intel® 41210 devices (including add-in cards) by setting the Completion Timeout Timer Disable bit in the Vendor Specific command register (D2-7:F0:R045h bit 3) ...
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... Intel recommends an algorithm that will issue an Secondary Bus Reset upon a link training failure Workaround: for 2ms. The algorithm should support at least three iterations of Secondary Bus Resets. Status: For the steppings effected, see the Summary Table of Changes. 26. SKP ordered set may not be sent within required interval ...
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... BIOS updates are required to support PIC mode. Use of PCI Express adapters is not recommended. PCI Express devices down on the motherboard are supported if they are single function devices or have their IOAPIC enabled. Refer to your Intel representative for details. Status: For the steppings effected, see the Summary Table of Changes. ...
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... The PCI Express specification for Electrical Idle at the receiver peak-peak differential, and characterization of the MCH indicates that some lanes on some devices are marginal with respect to this specification. While L1 failures should be exceedingly rare, Intel recognize that this specification is difficult to meet, and acknowledge the exposure Systems with sufficient noise at the MCH receivers and a BIOS profile that escalates the “ ...
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... The E7520 Memory Controller may not detect particular DQS lanes toggling for all DLL offsets Implication: during the receive calibration at cold temps. Upgrade the E7520 Memory Reference Code to version 1.05. Workaround: Status: For the steppings affected, see the Summary Table of Changes. 20 ® Intel E7520 Memory Controller Hub (MCH) Specification Update ...
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... Specification Changes There are no Specification Changes in this revision of the Specification Update. ® Intel E7520 Memory Controller Hub (MCH) Specification Update Specification Changes 21 ...
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... This may result in a measurable performance degradation within the remap range for latency-sensitive benchmarks that are run on lightly loaded systems. This latency difference disappears when latency-sensitive benchmarks are run on moderately to heavily loaded systems. 22 ® Intel E7520 Memory Controller Hub (MCH) Specification Update ...
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... Default Value: Bit Field Default & Access 31:14 00001h 13 R/W 12:0 048Ch ® Intel E7520 Memory Controller Hub (MCH) Specification Update 4C - 4Fh R/ bits 0000_648Ch Reserved 1b Interrupt Redirection Algorithm (XTPR LRU (least recently used within the lowest priority pool highest number in lowest priority pool, default ...