NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 7

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

Errata
Intel
No.
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
11
1
2
3
4
5
6
7
8
9
®
E7520 Memory Controller Hub (MCH) Specification Update
C1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Stepping
C2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
C4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Plan Fix
Plan Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Fixed
Status
DMA channel source address checking error
Data corruption after an illegal front side bus configuration Write
Improper ECC and Memory Initialization while in Symmetric mode
Single Channel ECC Error Injection issue
PCI Express* add-in card presence detect state misreported
Incorrect PCI Express Link/Lane numbers driven in degraded link
PCI Express Compliance Mode issue
PCI Express Hot-Plug MSI interrupt issue
PCI Express link training failures on hot reset
Subsystem Identification and Subsystem Vendor Identification register issue
MCH responds with illegal access on the Hub Interface for 32 GB configurations
MCH hang on PCI Express enhanced configurations to non-existent devices causes hang
Spurious errors logged during link training events
DDR2 write offset issue
DMA MSI interrupt issue
SEC and DED error counters aliased in mirror mode
HiLoCS bit not readable in memory error address registers
MCH transitions from Polling.Active prematurely
Non-fatal completion timeout errors observed on PCI Express devices
SEC errors may be reported on opposite channel’s error registers in memory mirroring mode
MCH fails to train when non-TS1/TS2 training sequences are received
DIMM sparing issue with demand scrub enabled
Configuration transaction may be ignored in MCH when Configuration Request Retry Status is
enabled in PCI Express to PCI/PCI-X bridges
PCI Express Hot-Plug indicator blink causes extra SMBus write
PCI Express x4, x8 links may train down to lower width
SKP ordered set may not be sent within required interval
END symbol omitted from the last PM_Request_Ack DLLP while entering L2 state on x1 PCI
Express link
System hang may occur when entering S4 and S5 power states
Transposed interrupt messages across Hub Interface
Completion timeout errors in the presence of heavy PCI Express peer-to-peer traffic
SMBDAT and SMBCLK signals pulled down in S5
Multiple PCI Express protocol errors may result in fatal receiver overflow
System marginalities may result in spurious link-down error events on power state changes
Possible loss of Hot-swap Power Fault Event in dual PCI Express Hot-swap port
configurations
Memory initialization may fail at low temperatures
ERRATA
Summary Table of Changes
7