NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 19

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

Workaround:
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Intel
®
E7520 Memory Controller Hub (MCH) Specification Update
A mux can be incorporated into the SMBus to disconnect the MCH when the platform goes into the
S5 state.
For the steppings effected, see the Summary Table of Changes.
Multiple PCI Express protocol errors may result in fatal receiver overflow
If a PCI Express device connected to the MCH generates multiple transaction layer protocol errors,
including, unexpected completion packets or malformed transaction layer packets (TLPs) that
otherwise pass all link-layer error checking, and have the correct alignment on the interface, the
MCH may experience a fatal receiver overflow.
If the above conditions are met, The MCH may detect and log a “fatal” receiver overflow error.
MCH behavior in the presence of this error is consistent with the specification, in that continued
operation on the port after such an error may be unreliable.
Intel recommends avoiding use of PCI Express devices that generate unexpected completion or
malformed TLP protocol violations. If this is unavoidable, the receiver overflow error detected by
the MCH may be escalated to a system event (e.g.: SERR#) that prevents continued operation on
the compromised link.
For the steppings effected, see the Summary Table of Changes.
System marginalities may result in spurious link-down error events on
power state changes
On system power state changes (S3, S4, and S5) PCI Express devices are placed in the D3 device
power state by the operating system, which results in automatic negotiation with the MCH to enter
the L1 link state. In systems where the cumulative noise present at the MCH receiver pins exceeds
the MCH receiver threshold for detecting Electrical Idle, the transition into L1 may fail to complete
normally, ultimately resulting in a spurious link-down error from the MCH. If link down error (D2-
7:F0:R140h, bit 11) is escalated using a fatal system error (SERR#) mechanism, a blue-screen may
result on exposed systems.
The PCI Express specification for Electrical Idle at the receiver is 65 mV peak-peak differential,
and characterization of the MCH indicates that some lanes on some devices are marginal with
respect to this specification. While L1 failures should be exceedingly rare, Intel recognize that this
specification is difficult to meet, and acknowledge the exposure
Systems with sufficient noise at the MCH receivers and a BIOS profile that escalates the “link
down error” as a fatal system event may be exposed to blue-screen occurrence on system power
state transitions. Exposure to the error increases with the cumulative noise (platform noise + silicon
noise) present at the MCH receivers when the link is in Electrical Idle. Systems utilizing a BIOS
configuration that does not escalate the “link down error” as a fatal error are not exposed.
Custom operating systems or future operating systems that independently manage the power state
of PCI Express devices outside the scope of system power state transitions would be similarly
exposed to link-down errors via the same mechanism. In cases where the destination power state on
the attached device is between D0 and D3, any such link-down event constitutes a real error from
which software may only recover by fully reconfiguring the devices below the affected link.
None
For the steppings affected, see the Summary Table of Changes.
Errata
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