NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 17

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

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Intel
®
E7520 Memory Controller Hub (MCH) Specification Update
Intel recommends an algorithm that will issue an Secondary Bus Reset upon a link training failure
for 2ms. The algorithm should support at least three iterations of Secondary Bus Resets.
For the steppings effected, see the Summary Table of Changes.
SKP ordered set may not be sent within required interval
During Link Recovery on a PCI Express port, the MCH may fail to transmit a SKP ordered set
within the required time interval as defined in the PCI Express 1.0a Specification if a TLP or DLLP
was pending when the link entered Recovery.Idle state.
If the receiving device depends upon receipt of a SKP ordered set to progress through Link
Recovery, a timeout will occur resulting in Link Down and automatic reinitialization of the PCI
Express link. A link transitions through Recovery only under exceptional operational conditions.
Following the Link Recovery timeout and reinitialization, the link should resume normal operation
unless the original Link Recovery condition was entered as a result of a hard failure mechanism.
None
For the steppings effected, see the Summary Table of Changes.
END symbol omitted from the last PM_Request_Ack DLLP while entering L2
state on x1 PCI Express link
When a x1 link transitions into the L2 state, the MCH may fail to transmit the END symbol of the
last PM_Request_Ack DLLP.
If a downstream device expects an END symbol in the last PM_Request_Ack DLLP from the
MCH, it may incorrectly decode the electrical ordered set that follows. Endpoints should expect the
COM symbol in the electrical ordered set to indicate a final confirmation to transition the link to
the L2 state.
None
For the steppings effected, see the Summary Table of Changes.
System hang may occur when entering S4 and S5 power states
When the system is transitioning into the S4 or S5 state, the MCH may fail to respond to an ICH
power management handshake event resulting in a system lock. Specifically, when the duration
between the rising edge of HICLK and the preceding rising edge of HCLKIN is between 1.6ns -
2.7ns when measured at the MCH pins, it is possible to encounter this erratum. This also implies
that if a platform is outside this range, this erratum will not be encountered.
When this failure occurs the system will maintain power and remain unresponsive indefinitely.
Once the system becomes unresponsive after encountering this erratum, it will only resume
operation after an AC power cycle or an unconditional powerdown.
Under normal operation, a transition into S3-S5 will have the following processor bus signature:
In the failing case steps 1 and 2 are observed, but step 3 is not.
System may hang during a power management transition.
Refer to your Intel Representative for workaround details.
For the steppings effected, see the Summary Table of Changes.
1. ICH asserts STPCLK# to the processor.
2. Processor issues a Stop Grant Acknowledge transaction on the processor bus.
3. ICH asserts SLP# to the processor.
Errata
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