NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 15

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

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Intel
®
E7520 Memory Controller Hub (MCH) Specification Update
SEC errors may be reported on opposite channel’s error registers in
memory mirroring mode
In memory mirroring mode the MCH may report SEC errors on opposite channels depending on
the state of SA15 and the DDRCSR FSM Mirror State Transition Qualifier (Device 0, Function 0,
Offset 9A-9Bh bits 11:10). Channel A SEC errors may be reported in Channel B error registers and
vice versa. Single bit errors occurring on Channel A would set bit 8 instead of bit 0 of both the
DRAM First Error (DRAM_FERR, Device 0, Function 1, Offset 80-81h) and DRAM Next Error
(DRAM_NERR, Device 0, Function 1, Offset 82-83h) registers. This also applies to respective
SEC counter for the DIMMS in each channel. These registers are the DRAM_SEC_xx counters in
Device 0, Function 1. The errors are reported correctly when the primary copy is read.
Errors may be misreported in opposite channel’s error registers.
Refer to the E7520, E7320 and E7525 BIOS Specification Update for workaround details.
For the steppings effected, see the Summary Table of Changes.
MCH fails to train when non-TS1/TS2 training sequences are received
During the PCI Express training sequence, if a broken endpoint or a good endpoint on a broken
board has correct receiver termination on any lane and transmits signals on that lane that can be
seen at the MCH and are not valid TS1/TS2 training sequences, the MCH will fail to train that link
at all.
The PCI Express specification intends that, if some lanes are transmitting bogus data instead of
valid training sequences, those lanes should be treated as broken, and the link should fail down to
an acceptable width (such as x1). If lane 0 were failing in this manner, the link would fail to train
per the PCI Express specification. If a higher-numbered lane were failing in this manner, the PCI
Express specification requires that the link attempt to train as a x1 on lane 0 - the MCH will not
train in this scenario.
Failures are anticipated to occur because of a broken transmitter/receiver path, or a silent
transmitter. None of those failure modes will cause the MCH to fail to train, since either the
receiver termination will be missing, or the transmitted signals will not be seen at the MCH. In
order to see invalid transmitted signals at the MCH, either a logic bug in the other PCI Express
endpoint would be required, or a signal integrity issue so severe as to make operation impossible.
None
For the steppings effected, see the Summary Table of Changes.
DIMM sparing issue with demand scrub enabled
When spare copy is in progress and a demand scrub (as a result of a demand fetch with a
correctable error) to an address resolving to the SCRUBLIM is performed, the process of spare
copy from the failing DIMM to spare DIMM may terminate prematurely.
A system hang may occur when the spare DIMM is brought “on-line” prematurely and bad data is
read from this DIMM. This condition is a result of the premature exit of the spare copy process.
BIOS should disable demand scrub prior to initiating spare copy and re-enable it after the data
migration is complete. Demand scrubbing can be enabled and disabled by updating the Scrub Limit
and Control Register (SCRUBLIM Device 8, Function 0, Offset C8-CBh bit 27).
For the steppings effected, see the Summary Table of Changes.
Errata
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