NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 18

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

Errata
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Transposed interrupt messages across Hub Interface
In cases where virtual wire interrupt messages (Assert/Deassert-INT[A, B, C, D]) received on PCI
Express are spuriously short (the deassert message is received before the assert message can be
forwarded by the MCH to the ICH), the MCH may infrequently transpose the interrupt assert and
deassert messages across the Hub Interface. Under normal conditions the MCH will forward an
interrupt assert message originating from a PCI Express port over the Hub Interface prior to
receiving or forwarding the corresponding deassert message. In the event that the transposition
occurs, the virtual wire is left asserted at the ICH when it is in fact de-asserted at the source. The
virtual wire will remain asserted until a subsequent interrupt on that same virtual wire arrives to
clear the condition. During the period where the virtual wire remains “stuck” asserted, spurious
interrupts will be forwarded to the processor(s).
Systems running with a single logical processor (most commonly in uni-processor configurations
when Hyper-Threading Technology is disabled) and operating in legacy PIC mode or virtual wire
mode A may hang under high I/O-driven interrupt stress. For systems operating in full APIC mode
where the number of virtual interrupt lines (intA, intB, etc.) used by all PCI Express adapters in a
system exceeds the number of logical processors (threads), the system may hang.
BIOS updates are required to support PIC mode. Use of PCI Express adapters is not recommended.
PCI Express devices down on the motherboard are supported if they are single function devices or
have their IOAPIC enabled. Refer to your Intel representative for details.
For the steppings effected, see the Summary Table of Changes.
Completion timeout errors in the presence of heavy PCI Express peer-to-
peer traffic
When a single PCI Express port receives a continuous stream of posted transactions targeting a
peer PCI Express port (as opposed to targeting memory), and the throughput into the sending port
is equal or higher than that of the destination port, the MCH will continuously grant the sending
port access to the target port until a break in the posted traffic occurs. Under these conditions, a
third PCI Express port attempting to send one or more posted transactions to the same target port
will be held off for an unbounded period of time (until a break occurs in the transmit stream from
the port currently granted access). Given the right mix of traffic to the port that is thus blocked, and
sufficient duration on the “continuous stream” of posted transactions at the target port, a
completion timeout error may occur on the port that is blocked. Note that outbound CPU traffic to
the target port and completions for inbound reads from the target port are not impacted by the
blocking mechanism; only competing peer transfers to the target will be stalled.
When PCI Express peer-to-peer transfers are sufficiently large and uninterrupted, and transfers are
initiated on multiple source ports targeting the same destination port, completion timeout errors
may occur. In order to trigger such a timeout, one of the peer source ports must be blocked for at
least 16.7 ms.
Limit the uninterrupted duration (total data payload size) for transfers between peer PCI Express
ports, such that no one continuous transfer will exceed a duration of 16.7 ms. For reference, each
x4 PCI Express port is capable of transferring well over 12 MB of data in 16.7 ms, thus an
uninterrupted blockage of such duration is not expected to occur unless extreme circumstances are
contrived.
For the steppings effected, see the Summary Table of Changes.
SMBDAT and SMBCLK signals pulled down in S5
According to SMBus Specification 2.0 the SMBDAT and SMBCLK signals are to float while in the
S5 state. Due to device protection circuitry these signals are pulled down while in the S5 state.
Devices on auxiliary power such as a BMC that share an SMBus connection with the MCH will not
be able to signal on the SMBus in the S5 state due to the signals being pulled down.
Intel
®
E7520 Memory Controller Hub (MCH) Specification Update